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DESCRIPTION:Title: Trend and Opportunities for High-Speed (GS/s) ADCs\n\nAb
 stract: Analog to digital converter (ADC) is a critical building block for
  most electronic systems. Many\nwideband electronic systems (such as wirel
 ess and wireline communications) favor digitization of analog\nsignal with
  increasing bandwidth (>GHz) and fidelity\; at the same time\, demand a lo
 w area/power\nconsumption. It leads to a great interest in high-speed ADCs
  in recent years. In this talk\, I will describe\nthe recent trend of high
 -speed (>GS/s) ADC. Many existing works leverage massively interleaved SAR
 \nADCs. On the other hand\, there are emerging opportunities to quantize t
 he analog signal in time domain\nwith high speed. I will introduce a few A
 DC architectures and/or techniques that demonstrate promises\nin achieving
  high conversion rate but at a low area and/or power consumption\, includi
 ng some silicon\nexamples developed in my research group.\n\nSpeaker(s): M
 ike Chen\, \n\nAgenda: \nNetworking: 4:00 pm - 5:00 pm (PT)\n\nPresentatio
 n: 5:00 pm - 6:00 pm (PT)\n\nRoom: 116\, Bldg: Bergin Hall\, 500 El Camino
  Real\, Santa Clara University\, Santa Clara\, California\, United States\
 , 95053
LOCATION:Room: 116\, Bldg: Bergin Hall\, 500 El Camino Real\, Santa Clara U
 niversity\, Santa Clara\, California\, United States\, 95053
ORGANIZER:geochen1@yahoo.com
SEQUENCE:41
SUMMARY:Title: Trend and Opportunities for High-Speed (GS/s) ADCs 
URL;VALUE=URI:https://events.vtools.ieee.org/m/467228
X-ALT-DESC:Description: <br /><div class="t pg-1m0 pg-1x1 pg-1h3 pg-1y2 pg-
 1ff1 pg-1fs0 pg-1fc0 pg-1sc0 pg-1ls0 pg-1ws0">Title: Trend and Opportuniti
 es for High-Speed (GS/s) ADCs</div>\n<div class="t pg-1m0 pg-1x1 pg-1h3 pg
 -1y2 pg-1ff1 pg-1fs0 pg-1fc0 pg-1sc0 pg-1ls0 pg-1ws0">&nbsp\;</div>\n<div 
 class="t pg-1m0 pg-1x1 pg-1h3 pg-1y3 pg-1ff1 pg-1fs0 pg-1fc0 pg-1sc0 pg-1l
 s0 pg-1ws0">Abstract: Analog to digital converter (ADC) is a critical buil
 ding block for most electronic systems. Many</div>\n<div class="t pg-1m0 p
 g-1x1 pg-1h3 pg-1y4 pg-1ff1 pg-1fs0 pg-1fc0 pg-1sc0 pg-1ls0 pg-1ws0">wideb
 and electronic systems (such as wireless and wireline communications) favo
 r digitization of analog</div>\n<div class="t pg-1m0 pg-1x1 pg-1h3 pg-1y5 
 pg-1ff1 pg-1fs0 pg-1fc0 pg-1sc0 pg-1ls0 pg-1ws0">signal with increasing ba
 ndwidth (&gt\;GHz) and fidelity\; at the same time\, demand a low area/pow
 er</div>\n<div class="t pg-1m0 pg-1x1 pg-1h3 pg-1y6 pg-1ff1 pg-1fs0 pg-1fc
 0 pg-1sc0 pg-1ls0 pg-1ws0">consumption. It leads to a great interest in hi
 gh-speed ADCs in recent years. In this talk\, I will describe</div>\n<div 
 class="t pg-1m0 pg-1x1 pg-1h3 pg-1y7 pg-1ff1 pg-1fs0 pg-1fc0 pg-1sc0 pg-1l
 s0 pg-1ws0">the recent trend of high-speed (&gt\;GS/s) ADC. Many existing 
 works leverage massively interleaved SAR</div>\n<div class="t pg-1m0 pg-1x
 1 pg-1h3 pg-1y8 pg-1ff1 pg-1fs0 pg-1fc0 pg-1sc0 pg-1ls0 pg-1ws0">ADCs. On 
 the other hand\, there are emerging opportunities to quantize the analog s
 ignal in time domain</div>\n<div class="t pg-1m0 pg-1x1 pg-1h3 pg-1y9 pg-1
 ff1 pg-1fs0 pg-1fc0 pg-1sc0 pg-1ls0 pg-1ws0">with high speed. I will intro
 duce a few ADC architectures and/or techniques that demonstrate promises</
 div>\n<div class="t pg-1m0 pg-1x1 pg-1h3 pg-1ya pg-1ff1 pg-1fs0 pg-1fc0 pg
 -1sc0 pg-1ls0 pg-1ws0">in achieving high conversion rate but at a low area
  and/or power consumption\, including some silicon</div>\n<div class="t pg
 -1m0 pg-1x1 pg-1h3 pg-1yb pg-1ff1 pg-1fs0 pg-1fc0 pg-1sc0 pg-1ls0 pg-1ws0"
 >examples developed in my research group.</div><br /><br />Agenda: <br /><
 p><strong>Networking: </strong>4:00 pm - 5:00 pm (PT)</p>\n<p><strong>Pres
 entation:</strong> 5:00 pm - 6:00 pm (PT)</p>
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