BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Chicago BEGIN:DAYLIGHT DTSTART:20250309T030000 TZOFFSETFROM:-0600 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:CDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20241103T010000 TZOFFSETFROM:-0500 TZOFFSETTO:-0600 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:CST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250225T031228Z UID:669F1568-E3FF-4723-82D8-0D1DEFB9BB8C DTSTART;TZID=America/Chicago:20250224T183000 DTEND;TZID=America/Chicago:20250224T200000 DESCRIPTION:Abstract:\n\nIt is computer architecture of my design\, of the RISC variety. It is an effort to achieve high code density\, deterministic execution and a uniform base for diversity. The 16-bit instructions are n ow running on a FPGA board\, with specifications for the 24 & 32-bit instr uctions written. The basic template is written and it is straightforward t o add more instructions.\n\nThat said\, I would welcome help: do trade-off studies (resource utilization and performance) on each additional instruc tion. Assembler\, compiler and other help is very much needed. As a sneak preview\, the architecture supports four data sizes and four data types. T hose interested can do experiments on:\n\nDifferent word sizes (16\, 18\, 24\, 32\, 36\, 42 ...)\n\nDifferent data types (unsigned\, two's complemen t\, sign & magnitude\, IEEE 754\, POSIT\, PT-floats\, 16-bit fixed point l ogarithms ...)\n\nDifferent implementations (single cycle\, pipelining\, m ultiple issue\, out-of-order … microarchitectures)\n\nBIO:\n\nJim Brakef ield became interested in computer architecture upon encountering the IBM 1620 and the CDC 1604 in his first semester of college. He went on to get degrees in Applied Math\, Computer Science and Electrical Engineering. His work experience was primarily real-time embedded software and circuit boa rd design. As a second career he pursued FPGAs and VHDL. He has one patent and has given many talks on a variety of STEM topics.\n\nRoom: BSIC 203\, Bldg: Blank Sheppard Innovation Center (BSIC)\, which is behind Richter M ath-Engineering Center (#22) in the map\, One Camino Santa Maria\, St. Mar y's University\, San Antonio\, Texas\, United States\, 78228 LOCATION:Room: BSIC 203\, Bldg: Blank Sheppard Innovation Center (BSIC)\, w hich is behind Richter Math-Engineering Center (#22) in the map\, One Cami no Santa Maria\, St. Mary's University\, San Antonio\, Texas\, United Stat es\, 78228 ORGANIZER:wluo@stmarytx.edu SEQUENCE:16 SUMMARY:A Digital Processor of RISC Variety Suitable for Architecture Explo ration URL;VALUE=URI:https://events.vtools.ieee.org/m/467923 X-ALT-DESC:Description: <br /><p><span style="background-color: rgb(251\, 2 38\, 184)\; color: rgb(224\, 62\, 45)\;"><strong>Abstract:</strong></span> </p>\n<p>It is computer architecture of my design\, of the RISC variety. I t is an effort to achieve high code density\, deterministic execution and a uniform base for diversity. The 16-bit instructions are now running on a FPGA board\, with specifications for the 24 &amp\; 32-bit instructions wr itten. The basic template is written and it is straightforward to add more instructions.&nbsp\;</p>\n<p>That said\, I would welcome help: do trade-o ff studies (resource utilization and performance) on each additional instr uction. &nbsp\;Assembler\, compiler and other help is very much needed. As a sneak preview\, the architecture supports four data sizes and four data types. &nbsp\;Those interested can do experiments on:&nbsp\;</p>\n<p>Diff erent word sizes (16\, 18\, 24\, 32\, 36\, 42 ...)</p>\n<p>Different data types (unsigned\, two's complement\, sign &amp\; magnitude\, IEEE 754\, PO SIT\, PT-floats\, 16-bit fixed point logarithms ...)</p>\n<p>Different imp lementations (single cycle\, pipelining\, multiple issue\, out-of-order &h ellip\; microarchitectures)</p>\n<p><span style="background-color: rgb(241 \, 196\, 15)\; color: rgb(224\, 62\, 45)\;"><strong>BIO:</strong></span></ p>\n<p>Jim Brakefield became interested in computer architecture upon enco untering the IBM 1620 and the CDC 1604 in his first semester of college. & nbsp\;He went on to get degrees in Applied Math\, Computer Science and Ele ctrical Engineering. &nbsp\;His work experience was primarily real-time em bedded software and circuit board design. &nbsp\;As a second career he pur sued FPGAs and VHDL. He has one patent and has given many talks on a varie ty of STEM topics.</p> END:VEVENT END:VCALENDAR