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DTSTART:20170312T030000
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DTSTAMP:20170911T161907Z
UID:EFF68A50-970C-11E7-8752-0050568D2FB3
DTSTART;TZID=America/Denver:20170922T134000
DTEND;TZID=America/Denver:20170922T144000
DESCRIPTION:Abstract: As Moore’s Law is slowing down and eventually appro
 aching an end for conventional CMOS\, new platforms for producing circuit-
 level innovation are desired. At the same time\, it is not desirable to th
 row away the existing Si-CMOS infrastructure to start new. The SMART-LEES 
 (Singapore MIT Alliance for Research and Technology – Low Energy Electro
 nic Systems) program is such a “vertical” innovative platform by “in
 serting” III-V layers into a conventional Si-CMOS foundry process. This 
 talk presents an overview of the SMART-LEES program as well as a unified c
 ompact model for generic GaN/InGaAs-based HEMTs in the context of the hybr
 id III-V + CMOS technology being developed for future heterogeneous integr
 ated circuits. The developed model has been implemented in a hybrid III-V/
 CMOS foundry PDK for designing heterogeneous circuits in III-V/Si co-integ
 rated technology.\n\nCo-sponsored by: Prof. T.S. Kalkur - Chair ECE Dept\,
  UCCS\n\nSpeaker(s): Dr. Xing Zhou\, \, Dr. Xing Zhou\, \n\nRoom: 105\, Bl
 dg: ENG Building \, University of Colorado at Colorado Springs\, 1420 Aust
 in Bluffs Parkway\, Colorado Springs\, Colorado\, United States\, 80918
LOCATION:Room: 105\, Bldg: ENG Building \, University of Colorado at Colora
 do Springs\, 1420 Austin Bluffs Parkway\, Colorado Springs\, Colorado\, Un
 ited States\, 80918
ORGANIZER:tkalkur@uccs.edu
SEQUENCE:0
SUMMARY:Future III-V/CMOS Co-Integrated Technology and Hybrid Circuit Desig
 n
URL;VALUE=URI:https://events.vtools.ieee.org/m/47004
X-ALT-DESC:Description: <br /><p>Abstract: As Moore&rsquo\;s Law is slowing
  down and eventually approaching an end for conventional CMOS\, new platfo
 rms for producing circuit-level innovation are desired.&nbsp\; At the same
  time\, it is not desirable to throw away the existing Si-CMOS infrastruct
 ure to start new.&nbsp\; The SMART-LEES (Singapore MIT Alliance for Resear
 ch and Technology &ndash\; Low Energy Electronic Systems) program is such 
 a &ldquo\;vertical&rdquo\; innovative platform by &ldquo\;inserting&rdquo\
 ; III-V layers into a conventional Si-CMOS foundry process.&nbsp\; This ta
 lk presents an overview of the SMART-LEES program as well as a unified com
 pact model for generic GaN/InGaAs-based HEMTs in the context of the hybrid
  III-V + CMOS technology being developed for future heterogeneous integrat
 ed circuits.&nbsp\; The developed model has been implemented in a hybrid I
 II-V/CMOS foundry PDK for designing heterogeneous circuits in III-V/Si co-
 integrated technology.</p>
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