BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20250309T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20251102T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250317T005358Z UID:296CC773-D79D-418D-8A6F-0AD28B445C8D DTSTART;TZID=America/Los_Angeles:20250313T180000 DTEND;TZID=America/Los_Angeles:20250313T203000 DESCRIPTION:Advanced Substrates for Chiplets and Heterogeneous Integration\ n\nJohn H Lau\, Unimicron Technology Corporation\n\nToday\, most of the pa ckage substrates for HPC driven by AI (artificial intelligence) are made b y the 2.5D IC integration. In general\, for 2.5D or CoWoS (chip on wafer o n substrate)\, the SoC and high bandwidth memories (HBMs) are supported by a TSV-interposer and then solder bump and underfill on a build-up package substrate. However\, because of the ever-increasing size of the TSV-inter poser\, the manufacture yield loss of the TSV-interposer is becoming unbea rable. The key players such as NVIDIA\, AMD\, Intel\, SK Hynix\, Samsung\, Micron\, TSMC\, etc. are working very hard to eliminate the TSV interpose r and put the HBMs directly on top of the SoC (3.3D IC integration). Front -end integration of some of the chiplets (before package heterogeneous int egration) can yield a smaller package size and a better performance (3.5D IC integration). In the past few years\, 2.3D IC integration or CoWoS-R is getting lots of traction. The motivation is to replace the TSV-interposer with a fan out fine metal L/S redistribution-layer (RDL)-substrate (or or ganic-interposer). In general\, for 2.3D\, the package substrate structure (hybrid substrate) consists of a build-up package substrate\, solder join ts with underfill\, and the organic-interposer. Today\, 2.3D is already in production. During IEEE/ECTC 2023\, TSMC published two papers on replacin g the large-size TSV-interposer by LSIs (local silicon interconnects\, i.e . Si bridges) and embedding the LSIs in fan-out RDL-substrate. TSMC called it CoWoS-L. Recently\, since Intel’s announcement (September 18\, 2023) on the glass core substrate for their one-trillion transistors to be ship ped before 2030\, glass core substrate has been a very hot topic. Since th e shipments of co-packaged optics (CPO) by Intel and Broadcom CPO has been getting lots of tractions. In this lecture\, the introduction\, recent ad vances\, and trends in the substrates of 3.5D IC integration\, 3.3D IC int egration\, 3D IC integration\, 2.5D IC integration\, 2.3D IC integration\, 2.1D IC integration\, 2D IC integration\, fan-out RDL\, embedded Si-bridg e\, CoWoS-R\, CoWoS-L\, CPO\, and glass core for HPC driven by AI will be discussed. Some recommendations will be provided.\n\nSpeaker(s): \, John L au\n\nAgenda: \n6:00-7:00PM Greeting and reception\n\n7:00-8:00PM Advanced Substrates for Chiplets and Heterogeneous Integration presentation by Joh n Lau\n\n8:00-8:30PM Questions and Discussion\n\nBldg: Building #1\, 15101 Alton Parkway\, Irvine\, California\, United States\, 92618 LOCATION:Bldg: Building #1\, 15101 Alton Parkway\, Irvine\, California\, Un ited States\, 92618 ORGANIZER:hichrih@ajiusa.com SEQUENCE:32 SUMMARY:Advanced Substrates for Chiplets and Heterogeneous Integration URL;VALUE=URI:https://events.vtools.ieee.org/m/471169 X-ALT-DESC:Description: <br /><p style="text-align: center\;"><strong>Advan ced Substrates for Chiplets and Heterogeneous Integration</strong></p>\n<p style="text-align: center\;"><strong>John H Lau\, Unimicron Technology Co rporation</strong></p>\n<p style="text-align: justify\;">Today\, most of t he package substrates for HPC driven by AI (artificial intelligence) are m ade by the 2.5D IC integration. In general\, for 2.5D or CoWoS (chip on wa fer on substrate)\, the SoC and high bandwidth memories (HBMs) are support ed by a TSV-interposer and then solder bump and underfill on a build-up pa ckage substrate. However\, because of the ever-increasing size of the TSV- interposer\, the manufacture yield loss of the TSV-interposer is becoming unbearable. The key players such as NVIDIA\, AMD\, Intel\, SK Hynix\, Sams ung\, Micron\, TSMC\, etc. are working very hard to eliminate the TSV inte rposer and put the HBMs directly on top of the SoC (3.3D IC integration). Front-end integration of some of the chiplets (before package heterogeneou s integration) can yield a smaller package size and a better performance ( 3.5D IC integration). In the past few years\, 2.3D IC integration or CoWoS -R is getting lots of traction. The motivation is to replace the TSV-inter poser with a fan out fine metal L/S redistribution-layer (RDL)-substrate ( or organic-interposer). In general\, for 2.3D\, the package substrate stru cture (hybrid substrate) consists of a build-up package substrate\, solder joints with underfill\, and the organic-interposer. Today\, 2.3D is alrea dy in production. During IEEE/ECTC 2023\, TSMC published two papers on rep lacing the large-size TSV-interposer by LSIs (local silicon interconnects\ , i.e. Si bridges) and embedding the LSIs in fan-out RDL-substrate. TSMC c alled it CoWoS-L. Recently\, since Intel&rsquo\;s announcement (September 18\, 2023) on the glass core substrate for their one-trillion transistors to be shipped before 2030\, glass core substrate has been a very hot topic . Since the shipments of co-packaged optics (CPO) by Intel and Broadcom CP O has been getting lots of tractions. In this lecture\, the introduction\, recent advances\, and trends in the substrates of 3.5D IC integration\, 3 .3D IC integration\, 3D IC integration\, 2.5D IC integration\, 2.3D IC int egration\, 2.1D IC integration\, 2D IC integration\, fan-out RDL\, embedde d Si-bridge\, CoWoS-R\, CoWoS-L\, CPO\, and glass core for HPC driven by A I will be discussed. Some recommendations will be provided.</p>\n<p style= "text-align: justify\;"><img src="https://events.vtools.ieee.org/vtools_ui /media/display/e0b6f409-cf69-4c5f-b51c-093157036168"></p><br /><br />Agend a: <br /><p>6:00-7:00PM Greeting and reception</p>\n<p>7:00-8:00PM Advance d Substrates for Chiplets and Heterogeneous Integration presentation by Jo hn Lau&nbsp\;</p>\n<p>8:00-8:30PM Questions and Discussion&nbsp\;</p> END:VEVENT END:VCALENDAR