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DTSTAMP:20250321T130902Z
UID:D904F4A0-32E7-4ABC-B314-D8213D1037FF
DTSTART;TZID=Europe/Warsaw:20250318T160000
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DESCRIPTION:The past two decades has seen proliferation of all-digital phas
 e-locked loops (ADPLL) for RF and high-performance frequency synthesis due
  to their clear benefits of flexibility\, reconfigurability\, transfer fun
 ction precision\, settling speed\, frequency modulation capability\, and a
 menability to integration with digital baseband and application processors
 . When implemented in nanoscale CMOS\, the ADPLL also exhibits advantages 
 of better performance\, lower power consumption\, lower area and cost over
  the traditional analog-intensive charge-pump PLL. In a typical ADPLL\, a 
 traditional VCO got directly replaced by a digitally controlled oscillator
  (DCO) for generating an output variable clock\, a traditional phase/frequ
 ency detector and a charge pump got replaced by a time-to-digital converte
 r (TDC) for detecting phase departures of the variable clock versus the fr
 equency reference (FREF) clock\, and an analog loop RC filter got replaced
  with a digital loop filter. The conversion gains of the DCO and TDC circu
 its are readily estimated and compensated using “free” but powerful di
 gital logic.\n\nCo-sponsored by: Silicon Creations\n\nRoom: 121\, Bldg: B1
 \, AGH University of Kraków\, Krakow\, Malopolskie\, Poland\, 30-059
LOCATION:Room: 121\, Bldg: B1\, AGH University of Kraków\, Krakow\, Malopo
 lskie\, Poland\, 30-059
ORGANIZER:krzysztof.kasinski@siliconcr.com
SEQUENCE:27
SUMMARY:Introduction to “All-Digital Phase-Locked Loops (ADPLL)” Part 2
  - Bogdan Staszewski - SSCS Chapter Poland Seminar
URL;VALUE=URI:https://events.vtools.ieee.org/m/472724
X-ALT-DESC:Description: <br /><div>\n<p>The past two decades has seen proli
 feration of all-digital phase-locked loops (ADPLL) for RF and high-perform
 ance frequency synthesis due to their clear benefits of flexibility\, reco
 nfigurability\, transfer function precision\, settling speed\, frequency m
 odulation capability\, and amenability to integration with digital baseban
 d and application processors. When implemented in nanoscale CMOS\, the ADP
 LL also exhibits advantages of better performance\, lower power consumptio
 n\, lower area and cost over the traditional analog-intensive charge-pump 
 PLL. In a typical ADPLL\, a traditional VCO got directly replaced by a dig
 itally controlled oscillator (DCO) for generating an output variable clock
 \, a traditional phase/frequency detector and a charge pump got replaced b
 y a time-to-digital converter (TDC) for detecting phase departures of the 
 variable clock versus the frequency reference (FREF) clock\, and an analog
  loop RC filter got replaced with a digital loop filter. The conversion ga
 ins of the DCO and TDC circuits are readily estimated and compensated usin
 g &ldquo\;free&rdquo\; but powerful digital logic.</p>\n</div>
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