BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20250309T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20251102T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250418T141255Z UID:44B1AB30-7626-4945-9678-E00E892C5254 DTSTART;TZID=America/Los_Angeles:20250416T163000 DTEND;TZID=America/Los_Angeles:20250416T174500 DESCRIPTION:Today\, most of the package substrates for HPC driven by AI (ar tificial intelligence) are made by the 2.5D IC integration. In general\, f or 2.5D or CoWoS (chip on wafer on substrate)\, the SoC and high bandwidth memories (HBMs) are supported by a TSV-interposer and then solder bump an d underfill on a build-up package substrate. However\, because of the ever -increasing size of the TSV-interposer\, the manufacturing yield loss of t he TSV-interposer is becoming unbearable. Front-end integration of some of the chiplets (before package heterogeneous integration) can yield a small er package size and a better performance (3.5D IC integration). In the pas t few years\, 2.3D IC integration or CoWoS-R is getting lots of traction. The motivation is to replace the TSV-interposer with a fan out fine metal L/S redistribution-layer (RDL)-substrate (or organic-interposer). In gener al\, for 2.3D\, the package substrate structure (hybrid substrate) consist s of a build-up package substrate\, solder joints with underfill\, and the organic-interposer. In this lecture\, the introduction\, recent advances\ , and trends in the substrates of 3.5D IC integration\, 3.3D IC integratio n\, 3D IC integration\, 2.5D IC integration\, 2.3D IC integration\, 2.1D I C integration\, 2D IC integration\, fan-out RDL\, embedded Si-bridge\, CoW oS-R\, CoWoS-L\, CPO\, and glass core for HPC driven by AI will be discuss ed. Some recommendations will be provided.\n\nSpeaker(s): \, John Lau\n\nB ldg: Qualcomm Building Q Auditorium\, 6455 Lusk Blvd\, San Diego\, Califor nia\, United States\, 92121 LOCATION:Bldg: Qualcomm Building Q Auditorium\, 6455 Lusk Blvd\, San Diego\ , California\, United States\, 92121 ORGANIZER:pthadesar@ieee.org SEQUENCE:19 SUMMARY:Advanced Substrates for Chiplets and Heterogeneous Integration URL;VALUE=URI:https://events.vtools.ieee.org/m/472889 X-ALT-DESC:Description: <br /><p class="MsoNormal">Today\, most of the pack age substrates for HPC driven by AI (artificial intelligence) are made by the 2.5D IC integration. In general\, for 2.5D or CoWoS (chip on wafer on substrate)\, the SoC and high bandwidth memories (HBMs) are supported by a TSV-interposer and then solder bump and underfill on a build-up package s ubstrate. However\, because of the ever-increasing size of the TSV-interpo ser\, the manufacturing yield loss of the TSV-interposer is becoming unbea rable. Front-end integration of some of the chiplets (before package heter ogeneous integration) can yield a smaller package size and a better perfor mance (3.5D IC integration). In the past few years\, 2.3D IC integration o r CoWoS-R is getting lots of traction. The motivation is to replace the TS V-interposer with a fan out fine metal L/S redistribution-layer (RDL)-subs trate (or organic-interposer). In general\, for 2.3D\, the package substra te structure (hybrid substrate) consists of a build-up package substrate\, solder joints with underfill\, and the organic-interposer. In this lectur e\, the introduction\, recent advances\, and trends in the substrates of 3 .5D IC integration\, 3.3D IC integration\, 3D IC integration\, 2.5D IC int egration\, 2.3D IC integration\, 2.1D IC integration\, 2D IC integration\, fan-out RDL\, embedded Si-bridge\, CoWoS-R\, CoWoS-L\, CPO\, and glass co re for HPC driven by AI will be discussed. Some recommendations will be pr ovided.</p> END:VEVENT END:VCALENDAR