BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT DTSTART:20250309T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20251102T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250408T163249Z UID:2EC6C554-AFD0-41E2-9DE0-21C0D5447A5C DTSTART;TZID=America/New_York:20250327T150000 DTEND;TZID=America/New_York:20250327T170000 DESCRIPTION:SSCS Toronto is pleased to host two incredible speakers for a d ouble feature distinguished lecture.\n\nThe first speaker who will present from 3:00pm to 4:00pm is Dr. Rabia Yazicigil. Her talk is:\n\nTitle: The Circuit Frontier: Innovating and Expanding ASIC Solutions for Enhanced Bio sensing and Seamless Wireless Communication\n\nAbstract: This talk will in troduce Cyber-Secure Biological Systems\, leveraging living sensors constr ucted from engineered biological entities seamlessly integrated with solid -state circuits. This unique synergy harnesses the advantages of biology w hile incorporating the reliability and communication infrastructure of ele ctronics\, offering a unique solution to societal challenges in healthcare and environmental monitoring. In this talk\, examples of Cyber-Secure Bio logical Systems\, such as miniaturized ingestible bioelectronic capsules f or gastrointestinal tract monitoring and hybrid microfluidic-bioelectronic systems for environmental monitoring\, will be presented.\n\nAdditionally \, I will introduce a universal noise-centric data decoding approach using GRAND that facilitates ultra-low-energy wireless communications\, a criti cal requirement for the success of these biological systems and numerous o ther applications. In this talk\, I will delve into the intricacies of int erdisciplinary approach for system design\, spotlighting the potential of energy-efficient integrated circuits in the domains of biosensing and wire less communications. These collaborative research projects involve MIT BE/ MechE\, BU ECE/BME\, and MIT RLE-Northeastern University.\n\nThe second sp eaker who will present from 4:00pm to 5:00pm is Dr. Alvin Loke. His talk i s:\nTitle: The Road to Gate-All-Around CMOS\n\nAbstract: Despite the much debated end of Moore's Law\, CMOS scaling still maintains economic relevan ce with 3nm finFET SoCs already in the marketplace for over a year and 2nm gate-all-around SoCs well into risk production. Modest feature size reduc tion and design/technology innovations co-optimized for primarily logic sc aling continue to offer compelling node-to-node power\, performance\, area \, and cost benefits. In this tutorial\, we will start with a walk through memory lane\, recounting a brief history of transistor evolution to motiv ate the migration from the planar MOSFET to the fully depleted FinFET. We will summarize the key process technology elements that have enabled the f inFET CMOS nodes\, highlighting the resulting device technology characteri stics and challenges. This will set the context for motivating the introdu ction of the gate-all-around device architecture\, namely nanoribbons or n anosheets\, and unveiling the magic of how these devices are fabricated.\n \nSpeaker(s): Rabia\, Alvin\n\nRoom: SF2202\, Bldg: Sandford Fleming Build ing\, 10 King's College Rd\, Toronto\, Ontario\, Canada\, M5S 3G4 LOCATION:Room: SF2202\, Bldg: Sandford Fleming Building\, 10 King's College Rd\, Toronto\, Ontario\, Canada\, M5S 3G4 ORGANIZER: SEQUENCE:46 SUMMARY:Distinguished Lecture Double Feature: Dr. Rabia Yazicigil and Dr. A lvin Loke URL;VALUE=URI:https://events.vtools.ieee.org/m/473421 X-ALT-DESC:Description: <br /><p>SSCS Toronto is pleased to host two incred ible speakers for a double feature distinguished lecture.</p>\n<p>The firs t speaker who will present from 3:00pm to 4:00pm is Dr. Rabia Yazicigil. H er talk is:</p>\n<p><strong>Title:</strong>&nbsp\;The Circuit Frontier: In novating and Expanding ASIC Solutions for Enhanced Biosensing and Seamless Wireless Communication</p>\n<p><strong>Abstract:</strong>&nbsp\;This talk will introduce Cyber-Secure Biological Systems\, leveraging living sensor s constructed from engineered biological entities seamlessly integrated wi th solid-state circuits. This unique synergy harnesses the advantages of b iology while incorporating the reliability and communication infrastructur e of electronics\, offering a unique solution to societal challenges in he althcare and environmental monitoring. In this talk\, examples of Cyber-Se cure Biological Systems\, such as miniaturized ingestible bioelectronic ca psules for gastrointestinal tract monitoring and hybrid microfluidic-bioel ectronic systems for environmental monitoring\, will be presented.</p>\n<p >Additionally\, I will introduce a universal noise-centric data decoding a pproach using GRAND that facilitates ultra-low-energy wireless communicati ons\, a critical requirement for the success of these biological systems a nd numerous other applications. In this talk\, I will delve into the intri cacies of interdisciplinary approach for system design\, spotlighting the potential of energy-efficient integrated circuits in the domains of biosen sing and wireless communications. These collaborative research projects in volve MIT BE/MechE\, BU ECE/BME\, and MIT RLE-Northeastern University.</p> \n<p>The second speaker who will present from 4:00pm to 5:00pm is Dr. Alvi n Loke. His talk is:</p>\n<div data-olk-copy-source="MessageBody"><strong> Title:&nbsp\;</strong>The Road to Gate-All-Around CMOS</div>\n<div>&nbsp\; </div>\n<div><span class="mark5ql3ola7u" data-markjs="true" data-ogac="" d ata-ogab="" data-ogsc="" data-ogsb=""><strong>Abstract:</strong> </span>De spite the much debated end of Moore's Law\, CMOS scaling still maintains e conomic relevance with 3nm finFET SoCs already in the marketplace for over a year and 2nm gate-all-around SoCs well into risk production. Modest fea ture size reduction and design/technology innovations co-optimized for pri marily logic scaling continue to offer compelling node-to-node power\, per formance\, area\, and cost benefits. In this tutorial\, we will start with a walk through memory lane\, recounting a brief history of transistor evo lution to motivate the migration from the planar MOSFET to the fully deple ted FinFET. We will summarize the key process technology elements that hav e enabled the finFET CMOS nodes\, highlighting the resulting device techno logy characteristics and challenges. This will set the context for motivat ing the introduction of the gate-all-around device architecture\, namely n anoribbons or nanosheets\, and unveiling the magic of how these devices ar e fabricated.</div> END:VEVENT END:VCALENDAR