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DESCRIPTION:[]\n\nIEEE EDS Distinguished Lecture\n\nEmerging High-Speed Nan
 oscale Interconnect Issues and Modelling Challenges\n\nProf. Ramachandra A
 char\, Ph. D.\, P. Eng.\,\n\nIEEE Fellow\, Fellow EIC\n\nProfessor\, Depar
 tment of Electronics\,\n\nCarleton University\, Ottawa\, Ontario - K1S 5B6
 \n\nEmail: achar@doe.carleton.ca\n\nURL: www.doe.carleton.ca/~achar\n\nAbs
 tract: With the increasing demands for higher signal speeds coupled with t
 he need for decreasing feature sizes\, interconnect related signal integri
 ty effects such as delay\, distortion\, reflections\, crosstalk\, ground b
 ounce and electromagnetic interference have become the dominant factors li
 miting the performance of high-speed systems. These effects can be diverse
  and can seriously impact the design performance at all hierarchical level
 s including integrated circuits\, printed circuit boards\, multi-chip modu
 les and backplanes. This talk provides a comprehensive approach for unders
 tanding the multidisciplinary problem of signal integrity: issues/modeling
 /analysis in high-speed design.\n\n[]\n\nCo-sponsored by: IEEE Electron De
 vices Society under its Distinguished Lecturer Program\n\nSpeaker(s): Ram 
 Achar\, \n\nAgenda: \n14:00: Welcome\n\n14:15: Lecture\n\n15:00 - 16:00 Q&amp;
 A and discussions\n\nRoom: GLC E 34\, Bldg: GLC \, ETH Zürich D-ITET\, Gl
 oriastrasse 35\, Zürich\, Switzerland\, Switzerland
LOCATION:Room: GLC E 34\, Bldg: GLC \, ETH Zürich D-ITET\, Gloriastrasse 3
 5\, Zürich\, Switzerland\, Switzerland
ORGANIZER:lbegon@ethz.ch
SEQUENCE:57
SUMMARY:IEEE Electron Devices Distinguished Lecture by Prof. Ram Achar
URL;VALUE=URI:https://events.vtools.ieee.org/m/474600
X-ALT-DESC:Description: &lt;br /&gt;&lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: cente
 r\;&quot; align=&quot;center&quot;&gt;&lt;strong&gt;&lt;em style=&quot;mso-bidi-font-style: normal\;&quot;&gt;&lt;spa
 n lang=&quot;EN-CA&quot; style=&quot;font-size: 16.0pt\; line-height: 115%\; color: black
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 vents.vtools.ieee.org/vtools_ui/media/display/5191d54a-106a-46c9-8836-adbb
 0b549c95&quot; alt=&quot;&quot; width=&quot;1024&quot; height=&quot;508&quot;&gt;&lt;/span&gt;&lt;/em&gt;&lt;/strong&gt;&lt;/p&gt;\n&lt;p c
 lass=&quot;MsoNormal&quot; style=&quot;text-align: center\;&quot; align=&quot;center&quot;&gt;&lt;strong&gt;&lt;em s
 tyle=&quot;mso-bidi-font-style: normal\;&quot;&gt;&lt;span lang=&quot;EN-CA&quot; style=&quot;font-size: 
 16.0pt\; line-height: 115%\; color: black\; mso-themecolor: text1\; mso-an
 si-language: EN-CA\;&quot;&gt;IEEE EDS Distinguished Lecture&lt;/span&gt;&lt;/em&gt;&lt;/strong&gt;&lt;
 /p&gt;\n&lt;p style=&quot;margin: 0cm\; text-align: center\;&quot; align=&quot;center&quot;&gt;&lt;strong&gt;
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 \;&quot;&gt;Emerging High-Speed Nanoscale Interconnect Issues and Modelling Challe
 nges &lt;/span&gt;&lt;/strong&gt;&lt;/p&gt;\n&lt;p style=&quot;margin: 0cm\; text-align: center\;&quot; a
 lign=&quot;center&quot;&gt;&lt;br&gt;&lt;!--[endif]--&gt;&lt;/p&gt;\n&lt;p style=&quot;margin: 0cm\; text-align: 
 center\;&quot; align=&quot;center&quot;&gt;&lt;strong&gt;&lt;span lang=&quot;EN-CA&quot; style=&quot;font-size: 12.0
 pt\; font-family: &#39;Times New Roman&#39;\,serif\; color: windowtext\;&quot;&gt;Prof. Ra
 machandra Achar\, &lt;/span&gt;&lt;/strong&gt;&lt;span lang=&quot;EN-CA&quot; style=&quot;font-size: 12.
 0pt\; font-family: &#39;Times New Roman&#39;\,serif\;&quot;&gt;Ph. D.\, P. Eng.\, &lt;/span&gt;&lt;
 /p&gt;\n&lt;p style=&quot;margin: 0cm\; text-align: center\;&quot; align=&quot;center&quot;&gt;&lt;span la
 ng=&quot;EN-CA&quot; style=&quot;font-size: 12.0pt\; font-family: &#39;Times New Roman&#39;\,seri
 f\;&quot;&gt;IEEE Fellow\, Fellow EIC&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;marg
 in-bottom: 0cm\; text-align: center\;&quot; align=&quot;center&quot;&gt;&lt;span lang=&quot;EN-US&quot; s
 tyle=&quot;font-size: 12.0pt\; line-height: 115%\; font-family: &#39;Times New Roma
 n&#39;\,serif\; mso-bidi-theme-font: minor-bidi\;&quot;&gt;Professor\, Department of E
 lectronics\,&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;margin-bottom: 0cm\; 
 text-align: center\;&quot; align=&quot;center&quot;&gt;&lt;span lang=&quot;EN-US&quot; style=&quot;font-size: 
 12.0pt\; line-height: 115%\; font-family: &#39;Times New Roman&#39;\,serif\; mso-b
 idi-theme-font: minor-bidi\;&quot;&gt;Carleton University\, Ottawa\, Ontario - K1S
  5B6&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;margin-bottom: 0cm\; text-ali
 gn: center\;&quot; align=&quot;center&quot;&gt;&lt;span lang=&quot;EN-US&quot; style=&quot;font-size: 12.0pt\;
  line-height: 115%\; font-family: &#39;Times New Roman&#39;\,serif\; mso-bidi-them
 e-font: minor-bidi\;&quot;&gt;Email: &lt;/span&gt;&lt;span lang=&quot;EN-US&quot;&gt;&lt;a href=&quot;mailto:ach
 ar@doe.carleton.ca&quot;&gt;&lt;span style=&quot;font-size: 12.0pt\; line-height: 115%\; f
 ont-family: &#39;Times New Roman&#39;\,serif\; mso-bidi-theme-font: minor-bidi\;&quot;&gt;
 achar@doe.carleton.ca&lt;/span&gt;&lt;/a&gt;&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;m
 argin-bottom: 0cm\; text-align: center\;&quot; align=&quot;center&quot;&gt;&lt;span lang=&quot;EN-US
 &quot; style=&quot;font-size: 12.0pt\; line-height: 115%\; font-family: &#39;Times New R
 oman&#39;\,serif\; mso-bidi-theme-font: minor-bidi\;&quot;&gt;URL:&lt;span style=&quot;mso-tab
 -count: 1\;&quot;&gt;&amp;nbsp\;&amp;nbsp\; &lt;/span&gt;&lt;/span&gt;&lt;span lang=&quot;EN-US&quot;&gt;&lt;a href=&quot;http
 ://www.doe.carleton.ca/~achar&quot;&gt;&lt;span style=&quot;font-size: 12.0pt\; line-heigh
 t: 115%\; font-family: &#39;Times New Roman&#39;\,serif\; mso-bidi-theme-font: min
 or-bidi\;&quot;&gt;www.doe.carleton.ca/~achar&lt;/span&gt;&lt;/a&gt;&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;Mso
 Normal&quot;&gt;&lt;strong&gt;&lt;span lang=&quot;EN-CA&quot; style=&quot;font-size: 12.0pt\; line-height:
  115%\; color: black\; mso-themecolor: text1\; mso-ansi-language: EN-CA\;&quot;
 &gt;&amp;nbsp\;&lt;/span&gt;&lt;/strong&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: just
 ify\;&quot;&gt;&lt;strong style=&quot;mso-bidi-font-weight: normal\;&quot;&gt;&lt;span lang=&quot;EN-US&quot; s
 tyle=&quot;font-size: 12.0pt\; line-height: 115%\;&quot;&gt;Abstract:&lt;/span&gt;&lt;/strong&gt;&lt;s
 pan lang=&quot;EN-US&quot; style=&quot;font-size: 12.0pt\; line-height: 115%\;&quot;&gt; With the
  increasing demands for higher signal speeds coupled with the need for dec
 reasing feature sizes\, interconnect related signal integrity effects such
  as delay\, distortion\, reflections\, crosstalk\, ground bounce and elect
 romagnetic interference have become the dominant factors limiting the perf
 ormance of high-speed systems. These effects can be diverse and can seriou
 sly impact the design performance at all hierarchical levels including int
 egrated circuits\, printed circuit boards\, multi-chip modules and backpla
 nes. This talk provides a comprehensive approach for understanding the mul
 tidisciplinary problem of signal integrity: issues/modeling/analysis in hi
 gh-speed design.&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;text-align: justi
 fy\;&quot;&gt;&lt;span lang=&quot;EN-US&quot;&gt;&amp;nbsp\;&lt;img src=&quot;https://events.vtools.ieee.org/v
 tools_ui/media/display/a589febd-10d1-4107-9988-0aeb7ceda6f6&quot; alt=&quot;&quot; width=
 &quot;1024&quot; height=&quot;452&quot;&gt;&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot; style=&quot;margin-bottom
 : 0cm\; text-align: justify\;&quot;&gt;&lt;span lang=&quot;EN-US&quot; style=&quot;font-size: 12.0pt
 \; line-height: 115%\;&quot;&gt;&amp;nbsp\;&lt;/span&gt;&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;br /&gt;&lt;p&gt;14:
 00: Welcome&lt;/p&gt;\n&lt;p&gt;14:15: Lecture&lt;/p&gt;\n&lt;p&gt;15:00 - 16:00 Q&amp;amp\;A and disc
 ussions&lt;/p&gt;\n&lt;p&gt;&amp;nbsp\;&lt;/p&gt;
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