BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT DTSTART:20250309T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20251102T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250331T160954Z UID:7B7EC30A-044E-4C34-809C-7F23BBACE5D4 DTSTART;TZID=America/New_York:20250325T133000 DTEND;TZID=America/New_York:20250325T170000 DESCRIPTION:Despite the much debated end of Moore's Law\, CMOS scaling stil l maintains economic primacy with 3-nm FinFET SoCs already in the marketpl ace for several years and 2-nm gate-all-around SoCs anticipated this year. Modest feature size reduction and design/technology innovations co-optimi zed for primarily logic scaling continue to offer compelling node-to-node power\, performance\, area\, and cost benefits. In this tutorial\, we will start with a walk through memory lane\, recounting a brief history of tra nsistor evolution to motivate the migration from the planar MOSFET to the fully depleted FinFET. We will summarize the key process technology elemen ts that have enabled FinFET CMOS nodes\, highlighting the resulting device technology characteristics and challenges. This will set the stage for mo tivating the gate-all-around (GAA) transistor architecture\, namely nanori bbons or nanosheets\, and unveiling the magic of how these devices are fab ricated. We will then shift to the challenges that CMOS scaling has impose d on analog design. To address the growing effort required for analog/mixe d-signal design\, we will cover design strategies on how analog design has adapted and thrived through decades of increasingly unfriendly scaling\, including the migration to heterogeneous integration.\n\nSpeaker(s): Alvin \, Alvin\n\nRoom: E7-7303/7363\, Bldg: E7\, University of Waterloo\, 200 U niversity Avenue West\, Waterloo\, Ontario\, Canada\, N2L 3G4 LOCATION:Room: E7-7303/7363\, Bldg: E7\, University of Waterloo\, 200 Unive rsity Avenue West\, Waterloo\, Ontario\, Canada\, N2L 3G4 ORGANIZER:jrlong@uwaterloo.ca SEQUENCE:13 SUMMARY:The Road to Gate-All-Around CMOS and Its Impact on Analog Design URL;VALUE=URI:https://events.vtools.ieee.org/m/474749 X-ALT-DESC:Description: <br /><p class="western" style="margin-bottom: 0cm\ ; line-height: 100%\;">Despite the much debated end of Moore's Law\, CMOS scaling still maintains economic primacy with 3-nm FinFET SoCs already in the marketplace for several years and 2-nm gate-all-around SoCs anticipate d this year. Modest feature size reduction and design/technology innovatio ns co-optimized for primarily logic scaling continue to offer compelling n ode-to-node power\, performance\, area\, and cost benefits. In this tutori al\, we will start with a walk through memory lane\, recounting a brief hi story of transistor evolution to motivate the migration from the planar MO SFET to the fully depleted FinFET. We will summarize the key process techn ology elements that have enabled FinFET CMOS nodes\, highlighting the resu lting device technology characteristics and challenges. This will set the stage for motivating the gate-all-around (GAA) transistor architecture\, n amely nanoribbons or nanosheets\, and unveiling the magic of how these dev ices are fabricated. We will then shift to the challenges that CMOS scalin g has imposed on analog design. To address the growing effort required for analog/mixed-signal design\, we will cover design strategies on how analo g design has adapted and thrived through decades of increasingly unfriendl y scaling\, including the migration to heterogeneous integration.</p> END:VEVENT END:VCALENDAR