BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20250309T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20251102T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250330T220809Z UID:7D88E31C-CEBA-4FA3-BF92-F84A920032DF DTSTART;TZID=America/Los_Angeles:20250327T183000 DTEND;TZID=America/Los_Angeles:20250327T203000 DESCRIPTION:ABSTRACT\n\nDigital twin (DT) is a relatively new technology co ncept with potential to improve semiconductor wafer\nprocessing. Developme nt of this technology has been evolutionary and a direct result of the con fluence\nof advances in high-performance computing\, network communication \, optimization techniques\, sensing\ntechnologies and the use of vast arr ay of sensors for process monitoring. Potential application of DT\ntechnol ogy to semiconductor equipment includes predictive maintenance\, fault det ection\, performance\nevaluation\, and chamber matching. Following a discu ssion of the DT concept\, this talk will focus on SC’s\nexperience with the most challenging aspect of DT technology – development of fast subsy stem models\nthat may be subsequently integrated to create a digital twin of a system. In most cases\, these low-order\nmodels have been developed f rom high-order\, high-fidelity physical models whose simulations run too\n slow for DT application. SC has an extensive background and experience in using various model-order\nreduction techniques to develop such fast model s of various semiconductor equipment such as RTP\,\nplasma etch\, CMP\, an d bake lithography systems. SC has successfully used these models for clos ed-loop\nreal time process control\, virtual sensing\, and chamber matchin g. Additionally\, we describe a couple of\nour research projects on non-ma nufacturing applications that are relevant. In one\, a low-order model of\ na complex system was developed by combining physics-based modeling with m achine learning (deep\nneural network\, or DNN) so that the user would be warned when changes to the system warranted that\nthe DNN be retrained. In another project\, a complete DT of a large structural system was develope d that\nis still in operation.\n\nSpeaker(s): Abbas\n\nAgenda: \n6:00 - 6: 30 - Networking and light dinner (for in person attendees)\n\n6:30 - 7:30 - Talk and Q & A\n\n7:30 - 8:00 - Wrap up and Networking\n\nRoom: 3116 (Th ird Floor)\, Bldg: SCDI\, Santa Clara University\, 500 El Camino Real\, Sa nta Clara\, California\, United States\, 95053\, Virtual: https://events.v tools.ieee.org/m/475484 LOCATION:Room: 3116 (Third Floor)\, Bldg: SCDI\, Santa Clara University\, 5 00 El Camino Real\, Santa Clara\, California\, United States\, 95053\, Vir tual: https://events.vtools.ieee.org/m/475484 ORGANIZER:maayoubi@scu.edu SEQUENCE:104 SUMMARY:The Role of Digital Twins in Semiconductor Manufacturing Control URL;VALUE=URI:https://events.vtools.ieee.org/m/475484 X-ALT-DESC:Description: <br /><p>ABSTRACT</p>\n<p>Digital twin (DT) is a re latively new technology concept with potential to improve semiconductor wa fer<br>processing. Development of this technology has been evolutionary an d a direct result of the confluence<br>of advances in high-performance com puting\, network communication\, optimization techniques\, sensing<br>tech nologies and the use of vast array of sensors for process monitoring. Pote ntial application of DT<br>technology to semiconductor equipment includes predictive maintenance\, fault detection\, performance<br>evaluation\, and chamber matching. Following a discussion of the DT concept\, this talk wi ll focus on SC&rsquo\;s<br>experience with the most challenging aspect of DT technology &ndash\; development of fast subsystem models<br>that may be subsequently integrated to create a digital twin of a system. In most cas es\, these low-order<br>models have been developed from high-order\, high- fidelity physical models whose simulations run too<br>slow for DT applicat ion. SC has an extensive background and experience in using various model- order<br>reduction techniques to develop such fast models of various semic onductor equipment such as RTP\,<br>plasma etch\, CMP\, and bake lithograp hy systems. SC has successfully used these models for closed-loop<br>real time process control\, virtual sensing\, and chamber matching. Additionall y\, we describe a couple of<br>our research projects on non-manufacturing applications that are relevant. In one\, a low-order model of<br>a complex system was developed by combining physics-based modeling with machine lea rning (deep<br>neural network\, or DNN) so that the user would be warned w hen changes to the system warranted that<br>the DNN be retrained. In anoth er project\, a complete DT of a large structural system was developed that <br>is still in operation.</p><br /><br />Agenda: <br /><p>6:00 - 6:30 - N etworking and light dinner (for in person attendees)</p>\n<p>6:30 - 7:30 - Talk and Q &amp\; A</p>\n<p>7:30 - 8:00 - Wrap up and Networking</p> END:VEVENT END:VCALENDAR