BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT DTSTART:20250309T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20251102T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250407T152110Z UID:5225B57A-0C38-4050-8F35-518CE764B8A7 DTSTART;TZID=America/New_York:20250404T140000 DTEND;TZID=America/New_York:20250404T150000 DESCRIPTION:Advanced Logic Scaling Using Monolithic 3D Integration\n\nMarko Radosavljevic\n\nIntel Corporation\n\nGroup leader in monolithic 3D integ ration in Components Research\nIEEE EDS Distinguished Lecturer\n\nAbstract : Transistor scaling has been one of the key engines driving the semicondu ctor industry for many decades\nnow. Beyond traditional (Dennard) scaling of physical dimensions and supply voltages\, innovations such as new mater ials and new architectures are being constantly and regularly deployed to enable introduction of new technology\nnodes.\nMain new architectural chan ges revolve around moving from planar device geometries to more 3D – fir st finFETs and most recently gate-all-around (GAA). These changes provide significant opportunities for scaling both due to\n(1) enabling gate pitch scaling because of improved short channel effects and (2) higher performa nce because device\nwidth is decoupled from the planar area. To enable the se architectures\, technology teams delivered many materials and\nprocess innovations due to increased physical aspect ratios as well as a need for very conformal depositions.\nExtending further into this third dimension\, researchers in academia\, consortia and industry are very interested\nin exploring device stacking as a means of increasing both functionality and logic scaling. While this appears as a natural\nnext step\, it also provid es an open wide space ripe for new materials\, integration approaches and applications. As such\nmuch of the early work has been focused on both (1) design technology co-optimization (DTCO) to identify needed ingredients t o enable scaling and (2) demonstrating those ingredients into physical imp lementations in Si.\nIn this presentation\, I will provide a general overv iew of monolithic 3D integration options\, provide a connection of\nthis r esearch is current and state-of-the-art and highlights experimental status \, challenges\, and prospects.\n\nBio: Marko Radosavljević received his P hD in physics from the University of Pennsylvania in 2001\, after which he spent 2 years as a\npostdoctoral researcher in the Physical Sciences Depa rtment at IBM T.J. Watson Research Center in Yorktown Heights\, NY.\nIn 20 03\, he joined Components Research (since renamed Technology Research) div ision of Intel Corporation\, Hillsboro\, OR.\nMarko’s external visibilit y has mostly been in researching different non-Si materials and transistor s\, such as InP\, InSb\, GaN material\nfamilies as well as carbon nanotube s for applications in logic\, RF and power delivery.\nSince 2019\, he is l eading a group in monolithic 3D integration in Components Research\, study ing how to enable new functionalities and provide ultimate density improve ments in Si microelectronics. He has served a larger community as editor o f EDL and\ncommittee member for various international conferences\, includ ing IEDM\, and is currently IEEE EDS Distinguished Lecturer and editor of IEEE Transactions on Materials for Electron Devices. He has received 2 Int el Achievement Awards (highest technical award\nwithin the company\, award ed annually)\, authored and co-authored many research manuscripts (includi ng the IEDM paper of the decade from 2001-2010 and VLSI test of time paper awarded in 2022)\, and holds numerous granted US and international patent s.is an Associate Professor and the Peter & Susanne Armstrong Distinguishe d Scholar in Electrical and Systems Engineering as well as Materials Scien ce and Engineering at the University of Pennsylvania (Penn). Deep complete d his undergraduate degree in Metallurgical Engineering from the Indian In stitute of Technology in Varanasi and his Ph.D. in Materials Science and E ngineering at Northwestern University. Deep was a Resnick Prize Postdoctor al Fellow at Caltech before joining Penn to start his own research group. His research interests broadly lie at the intersection of new materials\, surface science\, and solid-state devices for computing\, opto-electronics \, and energy harvesting applications\, in addition to the development of correlated and functional imaging techniques. Deep’s research has been w idely recognized with several awards from professional societies\, funding bodies\, industries as well as private foundations\, the most notable one s being the Optica Adolph Lomb Medal\, the Bell Labs Prize\, the AVS Peter Mark Memorial Award\, IEEE Photonics Society Young Investigator Award\, I EEE Nanotechnology Council Young Investigator Award\, IUPAP Early Career S cientist Prize in Semiconductors and the Alfred P. Sloan Fellowship. He ha s published over 150 journal papers with more than 21000 citations and hol ds several patents. He serves as the Associate Editor for ACS Nano Letters and has been appointed as a Distinguished Lecturer for the IEEE Nanotechn ology Council for 2025.\n\nPlace: 230A Davis Hall\, University at Buffalo\ , North Campus\, Buffalo\, NY 14260\n\nDate and time: April 4\, Friday 202 5\, 2pm EST\n\nHost: Vasili Perebeinos (vasilipe@buffalo.edu) on behalf of the IEEE Buffalo Section\n\nCo-sponsored by: IEEE Electron Devices Societ y (EDS) Distinguished Lecture - Marko Radosavljevic\n\n230A Davis Hall\, B uffalo\, New York\, United States\, 14260 LOCATION:230A Davis Hall\, Buffalo\, New York\, United States\, 14260 ORGANIZER:vasili_p@yahoo.com SEQUENCE:1 SUMMARY:Advanced Logic Scaling Using Monolithic 3D Integration URL;VALUE=URI:https://events.vtools.ieee.org/m/476666 X-ALT-DESC:Description: <br /><p><strong>Advanced Logic Scaling Using&nbsp\ ;Monolithic 3D Integration</strong></p>\n<p><strong>Marko Radosavljevic</s trong></p>\n<p>Intel Corporation</p>\n<p>Group leader in monolithic 3D int egration in Components Research<br>IEEE EDS Distinguished Lecturer</p>\n<p ><strong>Abstract:&nbsp\;</strong>Transistor scaling has been one of the k ey engines driving the semiconductor industry for many decades<br>now. Bey ond traditional (Dennard) scaling of physical dimensions and supply voltag es\, innovations such as new materials and new architectures are being con stantly and regularly deployed to enable introduction of new technology<br >nodes.<br>Main new architectural changes revolve around moving from plana r device geometries to more 3D &ndash\; first finFETs and most recently ga te-all-around (GAA). These changes provide significant opportunities for s caling both due to<br>(1) enabling gate pitch scaling because of improved short channel effects and (2) higher performance because device<br>width i s decoupled from the planar area. To enable these architectures\, technolo gy teams delivered many materials and<br>process innovations due to increa sed physical aspect ratios as well as a need for very conformal deposition s.<br>Extending further into this third dimension\, researchers in academi a\, consortia and industry are very interested<br>in exploring device stac king as a means of increasing both functionality and logic scaling. While this appears as a natural<br>next step\, it also provides an open wide spa ce ripe for new materials\, integration approaches and applications. As su ch<br>much of the early work has been focused on both (1) design technolog y co-optimization (DTCO) to identify needed ingredients to enable scaling and (2) demonstrating those ingredients into physical implementations in S i.<br>In this presentation\, I will provide a general overview of monolith ic 3D integration options\, provide a connection of<br>this research is cu rrent and state-of-the-art and highlights experimental status\, challenges \, and prospects.</p>\n<p>&nbsp\;</p>\n<p><strong>Bio:&nbsp\; </strong>Mar ko Radosavljević received his PhD in physics from the University of Penns ylvania in 2001\, after which he spent 2 years as a<br>postdoctoral resear cher in the Physical Sciences Department at IBM T.J. Watson Research Cente r in Yorktown Heights\, NY.<br>In 2003\, he joined Components Research (si nce renamed Technology Research) division of Intel Corporation\, Hillsboro \, OR.<br>Marko&rsquo\;s external visibility has mostly been in researchin g different non-Si materials and transistors\, such as InP\, InSb\, GaN ma terial<br>families as well as carbon nanotubes for applications in logic\, RF and power delivery.<br>Since 2019\, he is leading a group in monolithi c 3D integration in Components Research\, studying how to enable new funct ionalities and provide ultimate density improvements in Si microelectronic s. He has served a larger community as editor of EDL and<br>committee memb er for various international conferences\, including IEDM\, and is current ly IEEE EDS Distinguished Lecturer and editor of IEEE Transactions on Mate rials for Electron Devices. He has received 2 Intel Achievement Awards (hi ghest technical award<br>within the company\, awarded annually)\, authored and co-authored many research manuscripts (including the IEDM paper of th e decade from 2001-2010 and VLSI test of time paper awarded in 2022)\, and holds numerous granted US and international patents.is an Associate Profe ssor and the Peter &amp\; Susanne Armstrong Distinguished Scholar in Elect rical and Systems Engineering as well as Materials Science and Engineering at the University of Pennsylvania (Penn). Deep completed his undergraduat e degree in Metallurgical Engineering from the Indian Institute of Technol ogy in Varanasi and his Ph.D. in Materials Science and Engineering at Nort hwestern University. Deep was a Resnick Prize Postdoctoral Fellow at Calte ch before joining Penn to start his own research group. His research inter ests broadly lie at the intersection of new materials\, surface science\, and solid-state devices for computing\, opto-electronics\, and energy harv esting applications\, in addition to the development of correlated and fun ctional imaging techniques. Deep&rsquo\;s research has been widely recogni zed with several awards from professional societies\, funding bodies\, ind ustries as well as private foundations\, the most notable ones being the O ptica Adolph Lomb Medal\, the Bell Labs Prize\, the AVS Peter Mark Memoria l Award\, IEEE Photonics Society Young Investigator Award\, IEEE Nanotechn ology Council Young Investigator Award\, IUPAP Early Career Scientist Priz e in Semiconductors and the Alfred P. Sloan Fellowship. He has published o ver 150 journal papers with more than 21000 citations and holds several pa tents. He serves as the Associate Editor for ACS <em>Nano Letters&nbsp\;</ em>and has been appointed as a Distinguished Lecturer for the IEEE Nanotec hnology Council for 2025.</p>\n<p>&nbsp\;</p>\n<p><strong>Place:&nbsp\;</s trong>230A Davis Hall\, University at Buffalo\, North Campus\, Buffalo\, N Y 14260</p>\n<p><strong>Date and time: </strong>April 4\, Friday 2025\, 2p m EST</p>\n<p><strong>Host: </strong>Vasili Perebeinos (vasilipe@buffalo.e du) on behalf of the IEEE Buffalo Section</p> END:VEVENT END:VCALENDAR