BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
DTSTART:20250309T030000
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3
TZNAME:PDT
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BEGIN:STANDARD
DTSTART:20251102T010000
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11
TZNAME:PST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20250502T205829Z
UID:7ACB571B-66AA-4ED7-AEAA-5922950ED732
DTSTART;TZID=America/Los_Angeles:20250501T183000
DTEND;TZID=America/Los_Angeles:20250501T200000
DESCRIPTION:Chiplets are now the standard way to design chips at leading-ed
 ge nodes for applications such as AI and high-performance computing. Obvio
 us challenges include the new stage of heterogeneous integration\, the new
  bus that connects the chiplets\, and the new advanced packages that hold 
 it all together. No more afterthoughts\; packaging\, test\, integration\, 
 and manufacturing must all start right with the design. And design teams a
 nd foundry teams must work closely together to achieve the best result. Po
 wer\, thermal\, and other analyses must evaluate both individual chiplets 
 and the system-as-a-whole (including the package). The foundry will play a
  larger role than ever before because it will generally provide a choice o
 f packages and perform the integration\, and it will need fully tested (kn
 own good) dies to avoid wasting time and money on chips that fail inspecti
 on.\n\nSpeaker(s): Jawad Nasrullah\, \n\nRoom: 125\, Bldg: Heafey\, Santa 
 Clara University\, Santa Clara\, California\, United States\, Virtual: htt
 ps://events.vtools.ieee.org/m/477704
LOCATION:Room: 125\, Bldg: Heafey\, Santa Clara University\, Santa Clara\, 
 California\, United States\, Virtual: https://events.vtools.ieee.org/m/477
 704
ORGANIZER:edcheng@ieee.org
SEQUENCE:48
SUMMARY:Driving the AI Revolution with Chiplets: Got a Lot of Chip Designin
 ’ to Do
URL;VALUE=URI:https://events.vtools.ieee.org/m/477704
X-ALT-DESC:Description: <br /><p>Chiplets are now the standard way to desig
 n chips at leading-edge nodes for applications such as AI and high-perform
 ance computing. Obvious challenges include the new stage of heterogeneous 
 integration\, the new bus that connects the chiplets\, and the new advance
 d packages that hold it all together. No more afterthoughts\; packaging\, 
 test\, integration\, and manufacturing must all start right with the desig
 n. And design teams and foundry teams must work closely together to achiev
 e the best result. Power\, thermal\, and other analyses must evaluate both
  individual chiplets and the system-as-a-whole (including the package). Th
 e foundry will play a larger role than ever before because it will general
 ly provide a choice of packages and perform the integration\, and it will 
 need fully tested (known good) dies to avoid wasting time and money on chi
 ps that fail inspection.</p>
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