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VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Shanghai
BEGIN:STANDARD
DTSTART:19910915T010000
TZOFFSETFROM:+0900
TZOFFSETTO:+0800
TZNAME:CST
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BEGIN:VEVENT
DTSTAMP:20250326T021331Z
UID:27AB1B2E-4567-4BFC-A39A-49DBEBDA6C8B
DTSTART;TZID=Asia/Shanghai:20250306T140000
DTEND;TZID=Asia/Shanghai:20250306T151500
DESCRIPTION:Dr. Xing Zhou\, a semiconductor modeling expert\, presented a s
 eminar on the evolution of compact models—vital tools linking device beh
 avior to circuit design.\n\nHe traced model development from bulk MOSFETs 
 to FinFETs and GAA transistors\, highlighting the need for more accurate m
 odels as devices grow more complex.\n\nThe focus was on his Unified Region
 al Modeling (URM) approach\, which uses surface-potential-based equations 
 to unify models across device types and operating regions\, improving accu
 racy and reducing duplication.\n\nDr. Zhou demonstrated URM's application 
 to advanced devices like GaN and InGaAs HEMTs\, incorporating effects such
  as 2DEG\, trapping\, and self-heating. He introduced a scalable model val
 idated by simulations and measurements\, along with a practical subcircuit
  for circuit-level use.\n\nHe closed by addressing adoption challenges\, e
 mphasizing the disconnect between researchers\, EDA vendors\, foundries\, 
 and designers.\n\nCo-sponsored by: XJTLU Advanced Semiconductor Research C
 enter\n\nSpeaker(s): Dr. Xing Zhou\n\nRoom: 505\, Bldg: EE\, Xi’an Jiaot
 ong-Liverpool University\,  111 Ren’ai Road\, Suzhou\, Jiangsu\, China\,
  215123
LOCATION:Room: 505\, Bldg: EE\, Xi’an Jiaotong-Liverpool University\,  11
 1 Ren’ai Road\, Suzhou\, Jiangsu\, China\, 215123
ORGANIZER:kainlu.low@xjtlu.edu.cn
SEQUENCE:135
SUMMARY:Advancing Compact Modeling: Highlights from Dr. Xing Zhou’s IEEE 
 Seminar
URL;VALUE=URI:https://events.vtools.ieee.org/m/477806
X-ALT-DESC:Description: <br /><p class="MsoNormal" style="margin-bottom: 0i
 n\; text-indent: 0.3in\; line-height: normal\; text-align: center\;"><span
  style="font-size: 12.0pt\; font-family: 'Times New Roman'\,serif\; mso-fa
 reast-font-family: 'Times New Roman'\;"><img src="https://events.vtools.ie
 ee.org/vtools_ui/media/display/3b90d46a-baba-4644-8df6-b6b10152338d" width
 ="405" height="303"> <img src="https://events.vtools.ieee.org/vtools_ui/me
 dia/display/eb8b9be0-a4a5-42a3-a478-251d8d525fb6" width="404" height="303"
 ></span></p>\n<p class="" data-start="79" data-end="236">&nbsp\;</p>\n<p c
 lass="" data-start="79" data-end="236"><strong>Dr. Xing Zhou\, a semicondu
 ctor modeling expert\, presented a seminar on the evolution of compact mod
 els&mdash\;vital tools linking device behavior to circuit design.</strong>
 </p>\n<p class="" data-start="238" data-end="392"><strong>He traced model 
 development from bulk MOSFETs to FinFETs and GAA transistors\, highlightin
 g the need for more accurate models as devices grow more complex.</strong>
 </p>\n<p class="" data-start="394" data-end="605"><strong>The focus was on
  his Unified Regional Modeling (URM) approach\, which uses surface-potenti
 al-based equations to unify models across device types and operating regio
 ns\, improving accuracy and reducing duplication.</strong></p>\n<p class="
 " data-start="607" data-end="888"><strong>Dr. Zhou demonstrated URM's appl
 ication to advanced devices like GaN and InGaAs HEMTs\, incorporating effe
 cts such as 2DEG\, trapping\, and self-heating. He introduced a scalable m
 odel validated by simulations and measurements\, along with a practical su
 bcircuit for circuit-level use.</strong></p>\n<p class="" data-start="890"
  data-end="1021"><strong>He closed by addressing adoption challenges\, emp
 hasizing the disconnect between researchers\, EDA vendors\, foundries\, an
 d designers.</strong></p>
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