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DESCRIPTION:Silicon photonics are the semiconductor integration of EIC and 
 PIC on a silicon substrate (wafer) with complementary metal-oxide semicond
 uctor (CMOS) technology. On the other hand\, co-packaged optics (CPO) are 
 heterogeneous integration packaging methods to integrate the optical engin
 e (OE) which consists of photonic ICs (PIC) and the electrical engine (EE)
  which consists of the electronic ICs (EIC) as well as the switch ASIC (ap
 plication specific IC). The advantages of CPO are: (a) to reduce the lengt
 h of the electrical interface between the OE/EE (or PIC/EIC) and the ASIC\
 , (b) to reduce the energy required to drive the signal\, and (c) to cut t
 he latency which leads to better electrical performance. In the next few y
 ears\, we will see more implementations of a higher level of heterogeneous
  integration of PIC and EIC\, whether it is for performance\, form factor\
 , power consumption or cost. The content of this lecture is shown below.\n
 \n- Silicon Photonics\n- Data Centers\n- Optical Transceivers\n- Optical E
 ngine (OE) and Electrical Engine (EE)\n- OBO (on-board optics)\n- NPO (nea
 r-board optics)\n- CPO (co-packaged optics)\n- 3D Integration of the PIC a
 nd EIC\n- 3D Heterogeneous Integration of PIC and EIC\n- 3D Heterogeneous 
 Integration of ASIC Switch\, PIC and EIC\n- 3D Heterogeneous Integration o
 f ASIC Switch\, PIC and EIC with Bridges\n- 3D Heterogeneous Integration o
 f ASIC Switch\, EIC and PIC embedded in Glass-core Substrate\n- Summary an
 d Recommendations\n\nSpeaker(s): Dr. John H Lau\, \n\nBldg: HUB 350\, 350 
 Legget Dr\, Kanata\, Ontario\, Canada
LOCATION:Bldg: HUB 350\, 350 Legget Dr\, Kanata\, Ontario\, Canada
ORGANIZER:aabdella@ieee.org
SEQUENCE:20
SUMMARY:Co-Packaged Optics – 3D Heterogeneous Integration of Photonic IC 
 and Electronic IC
URL;VALUE=URI:https://events.vtools.ieee.org/m/479253
X-ALT-DESC:Description: <br /><p><img style="display: block\; margin-left: 
 auto\; margin-right: auto\;" src="https://events.vtools.ieee.org/vtools_ui
 /media/display/b7445b14-3cd5-4372-9a94-9f940939cad9" width="540" height="3
 60"></p>\n<p>Silicon photonics are the semiconductor integration of EIC an
 d PIC on a silicon substrate (wafer) with complementary metal-oxide semico
 nductor (CMOS) technology. On the other hand\, co-packaged optics (CPO) ar
 e heterogeneous integration packaging methods to integrate the optical eng
 ine (OE) which consists of photonic ICs (PIC) and the electrical engine (E
 E) which consists of the electronic ICs (EIC) as well as the switch ASIC (
 application specific IC). The advantages of CPO are: (a) to reduce the len
 gth of the electrical interface between the OE/EE (or PIC/EIC) and the ASI
 C\, (b) to reduce the energy required to drive the signal\, and (c) to cut
  the latency which leads to better electrical performance. In the next few
  years\, we will see more implementations of a higher level of heterogeneo
 us integration of PIC and EIC\, whether it is for performance\, form facto
 r\, power consumption or cost. The content of this lecture is shown below.
 </p>\n<ul>\n<li>Silicon Photonics</li>\n<li>Data Centers</li>\n<li>Optical
  Transceivers</li>\n<li>Optical Engine (OE) and Electrical Engine (EE)</li
 >\n<li>OBO (on-board optics)</li>\n<li>NPO (near-board optics)</li>\n<li>C
 PO (co-packaged optics)</li>\n<li>3D Integration of the PIC and EIC</li>\n
 <li>3D Heterogeneous Integration of PIC and EIC</li>\n<li>3D Heterogeneous
  Integration of ASIC Switch\, PIC and EIC</li>\n<li>3D Heterogeneous Integ
 ration of ASIC Switch\, PIC and EIC with Bridges</li>\n<li>3D Heterogeneou
 s Integration of ASIC Switch\, EIC and PIC embedded in Glass-core Substrat
 e</li>\n<li>Summary and Recommendations</li>\n</ul>
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