BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20250309T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20251102T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250427T002229Z UID:7CD2EEE0-C3E5-460A-8821-77BDAFA828B9 DTSTART;TZID=America/Los_Angeles:20250423T173000 DTEND;TZID=America/Los_Angeles:20250423T190000 DESCRIPTION:The Road to Gate-All-Around CMOS\n\nIEEE SSCS Distinguished Lec turer Dr. Alvin Loke\n[]\n\nAbstract: Despite the much debated end of Moor e's Law\, CMOS scaling still maintains economic relevance with 3nm finFET SoCs already in the marketplace for over a year and 2nm gate-all-around So Cs well into risk production. Modest feature size reduction and design/tec hnology innovations co-optimized for primarily logic scaling continue to o ffer compelling node-to-node power\, performance\, area\, and cost benefit s. In this tutorial\, we will start with a walk through memory lane\, reco unting a brief history of transistor evolution to motivate the migration f rom the planar MOSFET to the fully depleted FinFET. We will summarize the key process technology elements that have enabled the finFET CMOS nodes\, highlighting the resulting device technology characteristics and challenge s. This will set the context for motivating the introduction of the gate-a ll-around device architecture\, namely nanoribbons or nanosheets\, and unv eiling the magic of how these devices are fabricated.\n\nSpeaker biography : Alvin Loke is a Senior Principal Engineer at Intel\, San Diego\, working on analog design/technology co-optimization for Intel’s Angstrom-era CM OS. He has previously worked on CMOS nodes spanning 250nm to 2nm at Agilen t\, AMD\, Qualcomm\, TSMC\, and NXP. He received a BASc from the Universit y of British Columbia\, and MS and PhD from Stanford. After several years in CMOS process integration\, Alvin has since worked on analog/mixed-signa l design focusing on a variety of wireline links\, design/model/technology interface\, and analog design methodologies. Alvin has been an active IEE E Solid-State Circuits Society (SSCS) volunteer since 2003\, having served as Distinguished Lecturer\, AdCom Member\, CICC Committee Member\, Webina r Chair\, Denver and San Diego Chapter Chair\, as well as JSSC\, SSCL\, an d Solid-State Circuits Magazine Guest Editor. He currently serves as the V LSI Symposium Secretary and SSCS Global Chapters Chair. Alvin has authored invited publications including the CICC 2018 Best Paper and short courses at ISSCC\, VLSI Symposium\, CICC\, and BCICTS.\n\nPlease register to allo w for proper planning.\nParking structure located at 2585 Augustine Dr. 3- hour free parking\n\nSpeaker(s): Dr. Alvin Loke\, \n\nAgenda: \n5:30pm: Ne tworking\n\n6:00pm: Talk\n\n7:00pm: Event ends\n\n2510 Augustine Dr\, Sant a Clara\, CA 95054\, Santa Clara\, California\, United States\, 95054 LOCATION:2510 Augustine Dr\, Santa Clara\, CA 95054\, Santa Clara\, Califor nia\, United States\, 95054 ORGANIZER:pcaragiulo@ieee.org SEQUENCE:41 SUMMARY:The Road to Gate-All-Around CMOS URL;VALUE=URI:https://events.vtools.ieee.org/m/479669 X-ALT-DESC:Description: <br /><div>\n<div>\n<table style="border-collapse: collapse\; width: 100%\; background-color: #ffffff\; border: 1px none #FFF FFF\;" border="1"><colgroup><col style="width: 50%\;"><col style="width: 5 0%\;"></colgroup>\n<tbody>\n<tr>\n<td style="border-color: rgb(255\, 255\, 255)\;">\n<p><strong>The Road to Gate-All-Around CMOS</strong></p>\n<p>IE EE SSCS Distinguished Lecturer Dr. Alvin Loke</p>\n</td>\n<td style="text- align: center\; border-color: rgb(255\, 255\, 255)\;"><img src="https://ev ents.vtools.ieee.org/vtools_ui/media/display/9c3da497-bb2f-40f1-95ed-7dc39 62ffafa" alt="" width="228" height="255"></td>\n</tr>\n</tbody>\n</table>\ n</div>\n<div>&nbsp\;</div>\n<div><strong>Abstract:&nbsp\;</strong>Despite the much debated end of Moore's Law\, CMOS scaling still maintains econom ic relevance with 3nm finFET SoCs already in the marketplace for over a ye ar and 2nm gate-all-around SoCs well into risk production. Modest feature size reduction and design/technology innovations co-optimized for primaril y logic scaling continue to offer compelling node-to-node power\, performa nce\, area\, and cost benefits. In this tutorial\, we will start with a wa lk through memory lane\, recounting a brief history of transistor evolutio n to motivate the migration from the planar MOSFET to the fully depleted F inFET. We will summarize the key process technology elements that have ena bled the finFET CMOS nodes\, highlighting the resulting device technology characteristics and challenges. This will set the context for motivating t he introduction of the gate-all-around device architecture\, namely nanori bbons or nanosheets\, and unveiling the magic of how these devices are fab ricated.</div>\n<div>&nbsp\;</div>\n</div>\n<div><strong>Speaker biography : </strong>Alvin Loke is a Senior Principal Engineer at Intel\, San Diego\ , working on analog design/technology co-optimization for Intel&rsquo\;s A ngstrom-era CMOS. He has previously worked on CMOS nodes spanning 250nm to 2nm at Agilent\, AMD\, Qualcomm\, TSMC\, and NXP. He received a BASc from the University of British Columbia\, and MS and PhD from Stanford. After several years in CMOS process integration\, Alvin has since worked on anal og/mixed-signal design focusing on a variety of wireline links\, design/mo del/technology interface\, and analog design methodologies. Alvin has been an active IEEE Solid-State Circuits Society (SSCS) volunteer since 2003\, having served as Distinguished Lecturer\, AdCom Member\, CICC Committee M ember\, Webinar Chair\, Denver and San Diego Chapter Chair\, as well as JS SC\, SSCL\, and Solid-State Circuits Magazine Guest Editor. He currently s erves as the VLSI Symposium Secretary and SSCS Global Chapters Chair. Alvi n has authored invited publications including the CICC 2018 Best Paper and short courses at ISSCC\, VLSI Symposium\, CICC\, and BCICTS.</div>\n<div> &nbsp\;</div>\n<div>\n<p>Please register to allow for proper planning.<br> Parking structure located at 2585 Augustine Dr. &nbsp\;3-hour free parking </p>\n</div><br /><br />Agenda: <br /><p>5:30pm: Networking</p>\n<p>6:00pm : Talk</p>\n<p>7:00pm: Event ends</p> END:VEVENT END:VCALENDAR