BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Phoenix BEGIN:STANDARD DTSTART:19671029T010000 TZOFFSETFROM:-0600 TZOFFSETTO:-0700 TZNAME:MST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250525T210854Z UID:F1E73ED6-B552-463B-9BD9-0FEC6CE660B0 DTSTART;TZID=America/Phoenix:20250522T160000 DTEND;TZID=America/Phoenix:20250522T180000 DESCRIPTION:Abstract:\n\nWith the rapid developments in artificial intellig ence and other high performance computing applications\, future electronic systems need to provide significantly improved performance. One area wher e the performance demand has been scaling very aggressively is for interco nnecting different components and chiplets by means of system-in-packages with high-speed/high-bandwidth signaling. To address this demand\, future system-in-package architectures and designs require innovations in package technologies\, analysis and validation methods and tools\, and standardiz ation. This presentation will review some recent developments in advanced electronic packaging technologies that aim to provide significantly improv ed performance for both on- and off-package high-speed interconnects. It w ill also summarize some of the current challenges and solutions for the co rresponding electrical methodologies and metrologies. Finally\, recent pro gress on standardization of on-package high-speed signaling for seamless 2 /2.5/3D integration of chiplets will be presented with some thoughts on fu ture scaling and remaining challenges.\n\n[]\n\nBiography:\n\nKemal Aygün is a Fellow at Intel Foundry Technology Development organization\, where he has been leading the development of high-bandwidth package and socket t echnologies and modeling and characterization methodologies for on- and of f-package I/O interfaces. He has co-authored 5 book chapters\, more than 1 00 journal and conference publications\, and holds 180 patents. He was the General Chair of the 2020 IEEE Electrical Performance of Electronic Packa ging and Systems Conference. Dr. Aygün is an IEEE Fellow and has been act ing as a Distinguished Lecturer for the IEEE Electronics Packaging Society . He has a Ph.D. in Electrical and Computer Engineering from the Universit y of Illinois at Urbana-Champaign.\n\nDate: May 22\, 2025\n\nLocation: Int el CH6 (5000 W Chandler Blvd\, Chandler\, AZ 85226\, [Google Maps](https:/ /maps.app.goo.gl/v7A23eB8gyjkZsbq9?g_st=com.google.maps.preview.copy))\n\n Parking Instruction:\n\n- Location Pin: [https://maps.app.goo.gl/v7A23eB8g yjkZsbq9?g_st=com.google.maps.preview.copy](https://urldefense.com/v3/__ht tps://maps.app.goo.gl/v7A23eB8gyjkZsbq9?g_st=com.google.maps.preview.copy_ _\;!!IKRxdwAv5BmarQ!fKbtVshkaEa-T-BLgfcfOzZZVlt4Z6UmsHEp5kgHTLjv6MM8GiBOcV wMp3fxeLqidIri7GiMqxv5btk4rDcf7MTFwKRnlA$)\n- Please use the pin provided to enter the CH-6 building. Lobby is located at the entrance.\n- There is covered and uncovered parking available in front of this building accessib le to visitors.\n- Visitor parking spots are clearly marked. Please use th ese designated visitor parking spots. The parking block in red would be th e closest (Only few visitor spots available in Garage. None on 2nd floor). \n- More visitor parking is available in the lots which show green in the map below. (Safer option and more accessible).\n\n[]. []\n\nRegistration a t CH6 Lobby:\n\n- Registrants will be checked in prior arrival. Please ide ntify yourselves and wait at the lobby\, to be escorted to CH6-109 room\n\ nAgenda:\nRefreshments: 4:00-4:30pm\nSeminar Talk: 4:30-5:30pm\n\nRoom: 10 9\, Bldg: Intel CH6\, 5000 W Chandler Blvd\, Chandler\, Arizona\, United S tates\, 85226 LOCATION:Room: 109\, Bldg: Intel CH6\, 5000 W Chandler Blvd\, Chandler\, Ar izona\, United States\, 85226 ORGANIZER:Christopher.J.Bailey@asu.edu SEQUENCE:25 SUMMARY:2025 IEEE EPS Phoenix Section Seminar: Challenges and Solutions for High-Speed Signaling in Future System-in-Packages by Kemal Aygun (Intel) URL;VALUE=URI:https://events.vtools.ieee.org/m/480894 X-ALT-DESC:Description: <br /><p style="font-weight: 400\;"><strong>Abstrac t: </strong></p>\n<p style="font-weight: 400\;">With the rapid development s in artificial intelligence and other high performance computing applicat ions\, future electronic systems need to provide significantly improved pe rformance. One area where the performance demand has been scaling very agg ressively is for interconnecting different components and chiplets by mean s of system-in-packages with high-speed/high-bandwidth signaling. To addre ss this demand\, future system-in-package architectures and designs requir e innovations in package technologies\, analysis and validation methods an d tools\, and standardization. This presentation will review some recent d evelopments in advanced electronic packaging technologies that aim to prov ide significantly improved performance for both on- and off-package high-s peed interconnects. It will also summarize some of the current challenges and solutions for the corresponding electrical methodologies and metrologi es. Finally\, recent progress on standardization of on-package high-speed signaling for seamless 2/2.5/3D integration of chiplets will be presented with some thoughts on future scaling and remaining challenges.<strong>&nbs p\;</strong></p>\n<p><img class="alignnone size-medium wp-image-636" src=" https://r6.ieee.org/phoenix-eps/wp-content/uploads/sites/164/Kemal_photo-1 95x278.jpg" alt="" width="195" height="278"></p>\n<p style="font-weight: 4 00\;"><strong>Biography: </strong></p>\n<p style="font-weight: 400\;">Kema l Ayg&uuml\;n is a Fellow at Intel Foundry Technology Development organiza tion\, where he has been leading the development of high-bandwidth package and socket technologies and modeling and characterization methodologies f or on- and off-package I/O interfaces. He has co-authored 5 book chapters\ , more than 100 journal and conference publications\, and holds 180 patent s. He was the General Chair of the 2020 IEEE Electrical Performance of Ele ctronic Packaging and Systems Conference. Dr. Ayg&uuml\;n is an IEEE Fello w and has been acting as a Distinguished Lecturer for the IEEE Electronics Packaging Society. He has a Ph.D. in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign.</p>\n<p><strong>Date: May 22\, 2025</strong></p>\n<p><strong>Location:&nbsp\;</strong>Intel CH6 (5000 W Chandler Blvd\, Chandler\, AZ 85226\,&nbsp\;<a href="https://maps .app.goo.gl/v7A23eB8gyjkZsbq9?g_st=com.google.maps.preview.copy">Google Ma ps</a>)</p>\n<p><strong>Parking Instruction:&nbsp\;</strong></p>\n<ul type ="disc">\n<li class="MsoNormal">Location Pin:&nbsp\;<a href="https://urlde fense.com/v3/__https://maps.app.goo.gl/v7A23eB8gyjkZsbq9?g_st=com.google.m aps.preview.copy__\;!!IKRxdwAv5BmarQ!fKbtVshkaEa-T-BLgfcfOzZZVlt4Z6UmsHEp5 kgHTLjv6MM8GiBOcVwMp3fxeLqidIri7GiMqxv5btk4rDcf7MTFwKRnlA$" target="_blank " rel="noopener" data-saferedirecturl="https://www.google.com/url?q=https: //urldefense.com/v3/__https://maps.app.goo.gl/v7A23eB8gyjkZsbq9?g_st%3Dcom .google.maps.preview.copy__\;!!IKRxdwAv5BmarQ!fKbtVshkaEa-T-BLgfcfOzZZVlt4 Z6UmsHEp5kgHTLjv6MM8GiBOcVwMp3fxeLqidIri7GiMqxv5btk4rDcf7MTFwKRnlA$&amp\;s ource=gmail&amp\;ust=1747532475008000&amp\;usg=AOvVaw3IZk3YO0PSwXL21RQAzqe o">https://maps.app.goo.gl/<wbr>v7A23eB8gyjkZsbq9?g_st=com.<wbr>google.map s.preview.copy</a></li>\n<li class="MsoNormal">Please use the pin provided to enter the CH-6 building. Lobby is located at the entrance.</li>\n<li c lass="MsoNormal">There is covered and uncovered parking available in front of this building accessible to visitors.</li>\n<li class="MsoNormal">Visi tor parking spots are clearly marked. Please use these designated visitor parking spots. The parking block in red would be the closest (Only few vis itor spots available in Garage. None on 2<sup>nd</sup> floor).</li>\n<li c lass="MsoNormal">More visitor parking is available in the lots which show green in the map below. <strong>(Safer option and more accessible).</stron g></li>\n</ul>\n<p><img src="https://events.vtools.ieee.org/vtools_ui/medi a/display/93105444-20c0-445b-a60f-d3a10e82a8da" alt="" width="447" height= "421">. &nbsp\;<img src="https://events.vtools.ieee.org/vtools_ui/media/di splay/c6980136-204b-4187-9d72-9db08888b01a" alt="" width="459" height="419 "></p>\n<p class="MsoNormal"><strong>Registration at CH6 Lobby:</strong></ p>\n<ul type="disc">\n<li class="MsoNormal">Registrants will be checked in prior arrival. Please identify yourselves and wait at the lobby\, to be e scorted to CH6-109 room</li>\n</ul>\n<p><strong>Agenda:<br></strong>Refres hments: 4:00-4:30pm<br>Seminar Talk: 4:30-5:30pm</p> END:VEVENT END:VCALENDAR