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TZID:Asia/Taipei
BEGIN:STANDARD
DTSTART:19790930T230000
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TZOFFSETTO:+0800
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BEGIN:VEVENT
DTSTAMP:20260312T070328Z
UID:9F730D83-9DC7-4B4D-B8BA-DD53DB4CFC1E
DTSTART;TZID=Asia/Taipei:20250425T160000
DTEND;TZID=Asia/Taipei:20250425T170000
DESCRIPTION:Abstract:\nInteractions of IC chips and packaging structures di
 fferentiate the electronic performance among traditional 2D chips and adva
 nced 2.5D and 3D technologies. This presentation starts with their impacts
  on signal integrity (SI)\, power integrity (PI)\, electromagnetic compati
 bility (EMC) and electrostatic discharge protection (ESD)\, through indept
 h Si experiments with in-place noise measurements as well as full-chip and
  system level noise simulation. Additionally\, the backside of an integrat
 ed circuit (IC) chip\, more precisely\, the backside surface of its Silico
 n substrate\, provides open areas for circuit performance improvements and
  adversarial security attacks\, that are potentially contradictory or trad
 ed off in design for performance and security. The talk also explores the 
 security threats over the Si-substrate backside from both passive and acti
 ve side-channel attack viewpoints and then discusses countermeasure princi
 ples.\n\nBiography:\nMakoto Nagata (Senior Member\, IEEE) received the B.S
 . and M.S. degrees in physics from Gakushuin University\, Tokyo\, Japan\, 
 in 1991 and 1993\, respectively\, and the Ph.D. degree in electronics engi
 neering from Hiroshima University\, Hiroshima\, Japan\, in 2001. He was a 
 Research Associate at Hiroshima University from 1994 to 2002\, an Associat
 e Professor at Kobe University\, Kobe\, Japan\, from 2002 to 2009\, where 
 he was promoted to a Full Professor in 2009. His research interests includ
 e design techniques targeting high-performance mixed analog\, RF and digit
 al VLSI systems with particular emphasis on power/signal/substrate integri
 ty and electromagnetic compatibility\, testing and diagnosis\, 2.5D and 3D
  system\nintegration\, as well as their applications for hardware security
  and hardware safety\, and cryogenic electronics for quantum computing. Dr
 . Nagata is a Senior Member of IEICE. He has been a member of a variety of
  technical program committees of international conferences\, such as the S
 ymposium on VLSI Circuits (2002–2009)\, Custom Integrated Circuits Confe
 rence (2007–2009)\, Asian Solid-State Circuits Conference (2005–2009)\
 , International Solid-State Circuits Conference (2014-2022)\, European Sol
 id- State Circuits Conference (since 2020)\, and many others. He chaired t
 he Technology Directions subcommittee for International Solid-State Circui
 ts Conference (2018-2022) and served for an Executive Committee Member (20
 23-present). He was the Technical Program Chair (2010–2011)\, the Sympos
 ium Chair (2012–2013)\, and an Executive Committee Member (2014–2015) 
 for the Symposium on VLSI circuits. He was the IEEE Solid-State Circuits S
 ociety (SSCS) AdCom member (2020-2022)\, the distinguished lecturer (2020-
 2021\, and 2024-present)\, and currently serves as the chapters vice chair
  (2022-) of the society. He is an associate editor for IEEE Transactions o
 n VLSI Systems (since 2015).\n\nCo-sponsored by: SSCS Taipei Chapter\n\nAg
 enda: \n[]\n\nRoom: 124\, Bldg: Electrical Engineering 2\, NTU\,No. 1\, Se
 c. 4\, Roosevelt Rd.\, taipei\, T'ai-pei\, Taiwan
LOCATION:Room: 124\, Bldg: Electrical Engineering 2\, NTU\,No. 1\, Sec. 4\,
  Roosevelt Rd.\, taipei\, T'ai-pei\, Taiwan
ORGANIZER:yudoliao@nctu.edu.tw
SEQUENCE:21
SUMMARY:IC Chip and Packaging Interactions for Performance Improvements and
  Security Protections
URL;VALUE=URI:https://events.vtools.ieee.org/m/483115
X-ALT-DESC:Description: <br /><p><strong>Abstract:</strong><br>Interactions
  of IC chips and packaging structures differentiate the electronic perform
 ance among traditional 2D&nbsp\;chips and advanced 2.5D and 3D technologie
 s. This presentation starts with their impacts on signal integrity (SI)\,&
 nbsp\;power integrity (PI)\, electromagnetic compatibility (EMC) and elect
 rostatic discharge protection (ESD)\, through indepth&nbsp\;Si experiments
  with in-place noise measurements as well as full-chip and system level no
 ise simulation.&nbsp\;Additionally\, the backside of an integrated circuit
  (IC) chip\, more precisely\, the backside surface of its Silicon&nbsp\;su
 bstrate\, provides open areas for circuit performance improvements and adv
 ersarial security attacks\, that are&nbsp\;potentially contradictory or tr
 aded off in design for performance and security. The talk also explores th
 e security&nbsp\;threats over the Si-substrate backside from both passive 
 and active side-channel attack viewpoints and then&nbsp\;discusses counter
 measure principles.</p>\n<p><strong>Biography:</strong><br>Makoto Nagata (
 Senior Member\, IEEE) received the B.S. and M.S. degrees in physics from G
 akushuin University\, Tokyo\,&nbsp\;Japan\, in 1991 and 1993\, respectivel
 y\, and the Ph.D. degree in electronics engineering from Hiroshima Univers
 ity\, Hiroshima\,&nbsp\;Japan\, in 2001. He was a Research Associate at Hi
 roshima University from 1994 to 2002\, an Associate Professor at Kobe&nbsp
 \;University\, Kobe\, Japan\, from 2002 to 2009\, where he was promoted to
  a Full Professor in 2009. His research interests&nbsp\;include design tec
 hniques targeting high-performance mixed analog\, RF and digital VLSI syst
 ems with particular emphasis&nbsp\;on power/signal/substrate integrity and
  electromagnetic compatibility\, testing and diagnosis\, 2.5D and 3D syste
 m<br>integration\, as well as their applications for hardware security and
  hardware safety\, and cryogenic electronics for quantum&nbsp\;computing. 
 Dr. Nagata is a Senior Member of IEICE. He has been a member of a variety 
 of technical program committees of&nbsp\;international conferences\, such 
 as the Symposium on VLSI Circuits (2002&ndash\;2009)\, Custom Integrated C
 ircuits Conference&nbsp\;(2007&ndash\;2009)\, Asian Solid-State Circuits C
 onference (2005&ndash\;2009)\, International Solid-State Circuits Conferen
 ce (2014-2022)\, European Solid- State Circuits Conference (since 2020)\, 
 and many others. He chaired the Technology Directions&nbsp\;subcommittee f
 or International Solid-State Circuits Conference (2018-2022) and served fo
 r an Executive Committee Member&nbsp\;(2023-present). He was the Technical
  Program Chair (2010&ndash\;2011)\, the Symposium Chair (2012&ndash\;2013)
 \, and an Executive&nbsp\;Committee Member (2014&ndash\;2015) for the Symp
 osium on VLSI circuits. He was the IEEE Solid-State Circuits Society (SSCS
 )&nbsp\;AdCom member (2020-2022)\, the distinguished lecturer (2020-2021\,
  and 2024-present)\, and currently serves as the&nbsp\;chapters vice chair
  (2022-) of the society. He is an associate editor for IEEE Transactions o
 n VLSI Systems (since 2015).</p><br /><br />Agenda: <br /><p><img src="htt
 ps://events.vtools.ieee.org/vtools_ui/media/display/670d79d6-bb44-46cc-9f9
 9-ef6b09440651" alt=""></p>
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