BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:US/Pacific BEGIN:DAYLIGHT DTSTART:20250309T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20251102T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250523T171227Z UID:E80B9A49-BCA3-4C62-A54D-54A947F2630B DTSTART;TZID=US/Pacific:20250523T083000 DTEND;TZID=US/Pacific:20250523T100000 DESCRIPTION:IEEE SSCS Oregon Chapter May Meeting and Seminar\n\nJoin us for a talk from local Intel Labs Researchers\, Dr. Susnata Mondal and Dr. Sas hank Krishnamurthy\, on Friday\, May 23rd\, 2025. The seminar will be held from 8:30am to 10:00am (PST) via a Hybrid format. Please register for the meeting link and information.\n\nTopic:\n\nEnergy-Efficient Co-Packaged V CSEL-based High-Speed Optical Links\n\nAbstract:\n\nCo-packaged optics int egrate optical engines with compute (XPU) or switch chips\, drastically re ducing electrical losses and boosting link efficiency. At Intel Labs\, we developed two generations of co-packaged VCSEL(vertical-cavity surface-emi tting laser)-based optical transceivers for next-generation data center an d HPC applications. In the first generation\, a 4-channel optical engine —including VCSEL driver ICs\, VCSELs\, photodetectors\, TIAs\, and fiber termination—was co-packaged with electrical transceiver ICs (mimicking XPU) to deliver up to 64-Gb/s TX and 50-Gb/s RX per-channel NRZ data rates \, with outstanding energy efficiencies of 1.3 pJ/b and 1.5 pJ/b. Thes e industry-leading results were enabled by several circuit innovations: a novel complex-zero CTLE for VCSEL equalization\, low-power electrical TX\, resonant clock distribution\, Cherry-Hooper-based RX FFE\, and a low-nois e dual-clock-phase latch. The second-generation direct-drive transceiver a dvances to PAM-4 signaling\, reaching 108 Gb/s at a record-low 0.9  pJ /b\, thanks to a high-linearity coupled-inductor complex-zero CTLE for the VCSEL equalization and a high-linearity low-gain shunt-feedback TIA with active complex-zero CTLE for RX equalization.\n\nSpeaker Biographies:\n\nS usnata Mondal received the B.Tech and M.Tech degrees in Electronics Engine ering from IIT Kharagpur\, India\, in 2015\, and the Ph.D. degree in Elect rical and Computer Engineering from Carnegie Mellon University\, Pittsburg h\, in 2020. Since 2020\, he has been a Research Scientist with Intel Labs \, Hillsboro\, USA\, where he works on electrical/optical transceivers. Hi s current research interests include millimeter-wave circuit\, algorithm a nd system design for multi-antenna wireless\, and RF/mixed-signal design f or high-speed wireline/optical links. He was a recipient of the IEEE SSCS Predoctoral Achievement Award in 2019 and the A.G. Milnes Best Ph.D. Thesi s Award from Carnegie Mellon University in 2021. He was selected as the SS CS Rising-Star in ISSCC 2020.\n\nSashank Krishnamurthy received the B.Tech degree in Electrical Engineering from the IIT Madras\, Chennai\, India\, in 2015\, and the M.S. and Ph.D. degrees in Electrical Engineering from th e University of California at Berkeley\, CA\, in 2020. Since 2021\, he has been a Research Scientist with Intel Labs\, Hillsboro\, OR\, USA\, where he works on ultra high-speed integrated electrical/optical transceivers. H e has also been a Visiting Lecturer with the University of California at B erkeley. His current research interests include analog\, mixed-signal\, hi gh-speed digital\, RF\, and millimeter-wave circuit techniques.\n\nSpeaker (s): Dr. Susnata Mondal \, Dr. Sashank Krishnamurthy\n\nAgenda: \n8:30am - 10:00am: Professional/Career Seminar\n\nRoom: JFCC-119\, Bldg: Jones Farm Conference Center\, 2111 NE 25th Ave\, Hillsboro\, Oregon\, United State s\, 97124\, Virtual: https://events.vtools.ieee.org/m/484222 LOCATION:Room: JFCC-119\, Bldg: Jones Farm Conference Center\, 2111 NE 25t h Ave\, Hillsboro\, Oregon\, United States\, 97124\, Virtual: https://even ts.vtools.ieee.org/m/484222 ORGANIZER:rdorrance@ieee.org SEQUENCE:20 SUMMARY:IEEE SSCS Oregon Chapter May Meeting and Seminar (Hybrid) URL;VALUE=URI:https://events.vtools.ieee.org/m/484222 X-ALT-DESC:Description: <br /><p><span style="text-decoration: underline\; color: #000000\;">IEEE SSCS Oregon Chapter May Meeting and Seminar</span>< /p>\n<p><span style="color: #000000\;">Join us for a talk from local Intel Labs Researchers\, Dr. <span style="font-size: 11.0pt\; font-family: 'Apt os'\,sans-serif\; mso-fareast-font-family: 'Times New Roman'\; mso-bidi-fo nt-family: Aptos\; color: black\; mso-ansi-language: EN-US\; mso-fareast-l anguage: EN-US\; mso-bidi-language: AR-SA\;">Susnata Mondal and Dr. Sashan k Krishnamurthy\, </span></span><span style="color: #000000\;">on Friday\, May 23rd\, 2025. The seminar will be held from 8:30am to 10:00am (PST) vi a a Hybrid format. Please register for the meeting link and information.</ span></p>\n<p>&nbsp\;</p>\n<p><span style="color: #000000\;">Topic:</span> </p>\n<p><span style="font-size: 11.0pt\; font-family: 'Aptos'\,sans-serif \; mso-fareast-font-family: 'Times New Roman'\; mso-bidi-font-family: Apto s\; color: black\; mso-ansi-language: EN-US\; mso-fareast-language: EN-US\ ; mso-bidi-language: AR-SA\;">Energy-Efficient Co-Packaged VCSEL-based Hig h-Speed Optical Links</span></p>\n<p>&nbsp\;</p>\n<p><span style="color: # 000000\;">Abstract:</span></p>\n<p><span style="font-size: 11.0pt\; font-f amily: 'Aptos'\,sans-serif\; mso-fareast-font-family: 'Times New Roman'\; mso-bidi-font-family: Aptos\; color: black\; mso-ansi-language: EN-US\; ms o-fareast-language: EN-US\; mso-bidi-language: AR-SA\;">Co-packaged optics integrate optical engines with compute (XPU) or switch chips\, drasticall y reducing electrical losses and boosting link efficiency. At Intel Labs\, we developed two generations of co-packaged VCSEL(vertical-cavity surface -emitting laser)-based optical transceivers for next-generation data cente r and HPC applications. In the first generation\, a 4-channel optical engi ne&mdash\;including VCSEL driver ICs\, VCSELs\, photodetectors\, TIAs\, an d fiber termination&mdash\;was co-packaged with electrical transceiver ICs (mimicking XPU) to deliver up to 64-Gb/s TX and 50-Gb/s RX per-channel NR Z data rates\, with outstanding energy efficiencies of 1.3</span><span sty le="font-size: 11.0pt\; font-family: 'Arial'\,sans-serif\; mso-fareast-fon t-family: 'Times New Roman'\; color: black\; mso-ansi-language: EN-US\; ms o-fareast-language: EN-US\; mso-bidi-language: AR-SA\;"> </span><span st yle="font-size: 11.0pt\; font-family: 'Aptos'\,sans-serif\; mso-fareast-fo nt-family: 'Times New Roman'\; mso-bidi-font-family: Aptos\; color: black\ ; mso-ansi-language: EN-US\; mso-fareast-language: EN-US\; mso-bidi-langua ge: AR-SA\;">pJ/b and 1.5</span><span style="font-size: 11.0pt\; font-fami ly: 'Arial'\,sans-serif\; mso-fareast-font-family: 'Times New Roman'\; col or: black\; mso-ansi-language: EN-US\; mso-fareast-language: EN-US\; mso-b idi-language: AR-SA\;"> </span><span style="font-size: 11.0pt\; font-fam ily: 'Aptos'\,sans-serif\; mso-fareast-font-family: 'Times New Roman'\; ms o-bidi-font-family: Aptos\; color: black\; mso-ansi-language: EN-US\; mso- fareast-language: EN-US\; mso-bidi-language: AR-SA\;">pJ/b. These industry -leading results were enabled by several circuit innovations: a novel comp lex-zero CTLE for VCSEL equalization\, low-power electrical TX\, resonant clock distribution\, Cherry-Hooper-based RX FFE\, and a low-noise dual-clo ck-phase latch. The second-generation direct-drive transceiver advances to PAM-4 signaling\, reaching 108</span><span style="font-size: 11.0pt\; fon t-family: 'Arial'\,sans-serif\; mso-fareast-font-family: 'Times New Roman' \; color: black\; mso-ansi-language: EN-US\; mso-fareast-language: EN-US\; mso-bidi-language: AR-SA\;"> </span><span style="font-size: 11.0pt\; fo nt-family: 'Aptos'\,sans-serif\; mso-fareast-font-family: 'Times New Roman '\; mso-bidi-font-family: Aptos\; color: black\; mso-ansi-language: EN-US\ ; mso-fareast-language: EN-US\; mso-bidi-language: AR-SA\;">Gb/s at a reco rd-low 0.9</span><span style="font-size: 11.0pt\; font-family: 'Arial'\,sa ns-serif\; mso-fareast-font-family: 'Times New Roman'\; color: black\; mso -ansi-language: EN-US\; mso-fareast-language: EN-US\; mso-bidi-language: A R-SA\;"> </span><span style="font-size: 11.0pt\; font-family: 'Aptos'\,s ans-serif\; mso-fareast-font-family: 'Times New Roman'\; mso-bidi-font-fam ily: Aptos\; color: black\; mso-ansi-language: EN-US\; mso-fareast-languag e: EN-US\; mso-bidi-language: AR-SA\;"> pJ/b\, thanks to a high-linearity coupled-inductor complex-zero CTLE for the VCSEL equalization and a high-l inearity&nbsp\;low-gain shunt-feedback TIA with active complex-zero CTLE f or RX equalization.</span></p>\n<p>&nbsp\;</p>\n<p><span style="color: #00 0000\;">Speaker Biographies:</span></p>\n<p><strong>Susnata Mondal</strong > received the B.Tech and M.Tech degrees in Electronics Engineering from I IT Kharagpur\, India\, in 2015\, and the Ph.D. degree in Electrical and Co mputer Engineering from Carnegie Mellon University\, Pittsburgh\, in 2020. Since 2020\, he has been a Research Scientist with Intel Labs\, Hillsboro \, USA\, where he works on electrical/optical transceivers. His current re search interests include millimeter-wave circuit\, algorithm and system de sign for multi-antenna wireless\, and RF/mixed-signal design for high-spee d wireline/optical links. He was a recipient of the IEEE SSCS Predoctoral Achievement Award in 2019 and the A.G. Milnes Best Ph.D. Thesis Award from Carnegie Mellon University in 2021. He was selected as the SSCS Rising-St ar in ISSCC 2020.</p>\n<p><strong>Sashank Krishnamurthy</strong> received the B.Tech degree in Electrical Engineering from the IIT Madras\, Chennai\ , India\, in 2015\, and the M.S. and Ph.D. degrees in Electrical Engineeri ng from the University of California at Berkeley\, CA\, in 2020. Since 202 1\, he has been a Research Scientist with Intel Labs\, Hillsboro\, OR\, US A\, where he works on ultra high-speed integrated electrical/optical trans ceivers. He has also been a Visiting Lecturer with the University of Calif ornia at Berkeley. His current research interests include analog\, mixed-s ignal\, high-speed digital\, RF\, and millimeter-wave circuit techniques.< /p><br /><br />Agenda: <br /><p>8:30am - 10:00am: Professional/Career Semi nar</p> END:VEVENT END:VCALENDAR