BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Kolkata BEGIN:STANDARD DTSTART:19451014T230000 TZOFFSETFROM:+0630 TZOFFSETTO:+0530 TZNAME:IST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20251106T152113Z UID:A570D0D5-A698-4FB8-96E0-768F5F838EC4 DTSTART;TZID=Asia/Kolkata:20250227T093000 DTEND;TZID=Asia/Kolkata:20250228T180000 DESCRIPTION:The IEEE VLSI Student Branch (IEEE VLSI SB) is proud to have su ccessfully organized a two-day hands-on workshop on Static Timing Analysis (STA) on the 27th and 28th of February 2025. This workshop aimed to provi de participants with an in-depth understanding of STA concepts and their p ractical implementation in VLSI design. The session was conducted by Mr. N avneetha Krishnan\, a Senior Application Engineer from Entepule Technologi es\, who shared his extensive knowledge and experience in the field.\n\nDa y 1: Inauguration and Introduction to STA Tools\n\nThe workshop began with an inaugural session\, marking the commencement of an insightful and tech nical journey into STA. Mr. Navneetha Krishnan introduced the fundamentals of STA and its significance in VLSI circuit design. Participants were giv en an overview of the Cadence suite of tools used for STA\, including Temp us and Innovus. A live demonstration of these tools helped attendees famil iarize themselves with the workflow and their functionalities.\n\nOne of t he key hands-on activities of the first day was scripting an SDC (Synopsys Design Constraints) file. This exercise provided students with a fundamen tal understanding of how design constraints impact timing analysis and ove rall circuit performance. The session began with an explanation of various SDC commands and their role in defining timing constraints. Participants learned to specify clock definitions\, input and output delays\, false pat hs\, and multi-cycle paths using SDC syntax.\n\nTo reinforce their underst anding\, students engaged in practical scripting exercises where they defi ned constraints for a sample design. The session also included an introduc tion to scripting techniques using TCL (Tool Command Language)\, which is widely used in EDA tool automation. Students explored how TCL scripting en hances efficiency by automating repetitive design constraints and modifica tions.\n\nAdditionally\, the session emphasized best practices for writing SDC files\, ensuring compatibility with tools like Cadence Tempus and Inn ovus. By the end of the session\, participants had successfully created an d modified SDC files\, gaining hands-on experience in constraint definitio n. Later\, they began working on a counter program\, setting the foundatio n for detailed timing analysis and understanding its implications on setup and hold time constraints.\n\n.\n\nDay 2: Deep Dive into STA Concepts and Practical Analysis\n\nThe second day of the workshop commenced with a com prehensive presentation on the theoretical basics of STA. Topics such as s lack\, skew\, rise time\, fall time\, critical path analysis\, setup and h old time violations\, and clock timing analysis were thoroughly explained. This session provided participants with the fundamental understanding nec essary for effective STA implementation.\n\nFollowing the presentation\, p articipants engaged in a hands-on session focused on solving STA problems. They analyzed the critical paths of the counter program\, identified timi ng violations\, and worked on resolving setup and hold time violations. Cl ock timing analysis was also performed\, allowing students to gain deeper insights into optimizing design performance. The session was highly intera ctive\, with real-time problem-solving and discussions on various STA chal lenges encountered in industry applications.\n\nThe workshop concluded wit h an interactive Q&A session\, where students had the opportunity to clari fy doubts and discuss advanced topics related to STA. The knowledge impart ed over the two days provided participants with a strong foundation in STA \, equipping them with skills highly relevant to the VLSI industry.\n\nTo recognize the efforts and participation of attendees\, certificates were d istributed at the end of the event. IEEE VLSI SB extends its heartfelt gra titude to Mr. Navneetha Krishnan for his expert guidance and valuable insi ghts. The event was a resounding success\, providing students with the nec essary technical proficiency and hands-on experience in STA\, preparing th em for future challenges in VLSI design and development.\n\nThis workshop proved to be immensely beneficial to students\, helping them bridge the ga p between theoretical knowledge and industry practices. The practical expo sure to Cadence tools\, coupled with a deep understanding of STA concepts\ , has strengthened their technical foundation and enhanced their employabi lity in the semiconductor industry. The skills acquired during this worksh op will play a crucial role in their careers\, enabling them to tackle rea l-world challenges in VLSI design with confidence and proficiency.\n\nBang alore Institute Of Technology\, Department Of Electronics And Communicatio n\, Kr Road\, Vv Pura\, Bangalore\, Karnataka\, India\, 560004 LOCATION:Bangalore Institute Of Technology\, Department Of Electronics And Communication\, Kr Road\, Vv Pura\, Bangalore\, Karnataka\, India\, 56000 4 ORGANIZER:jalajas@ieee.org SEQUENCE:5 SUMMARY:Static Timing Analysis (STA) Workshop URL;VALUE=URI:https://events.vtools.ieee.org/m/484816 X-ALT-DESC:Description: <br /><p>The IEEE VLSI Student Branch (IEEE VLSI SB ) is proud to have successfully organized a two-day hands-on workshop on S tatic Timing Analysis (STA) on the 27th and 28th of February 2025. This wo rkshop aimed to provide participants with an in-depth understanding of STA concepts and their practical implementation in VLSI design. The session w as conducted by Mr. Navneetha Krishnan\, a Senior Application Engineer fro m Entepule Technologies\, who shared his extensive knowledge and experienc e in the field.</p>\n<p>Day 1: Inauguration and Introduction to STA Tools< br><img src="https://events.vtools.ieee.org/vtools_ui/media/display/da1d3b 4a-0e7e-4de7-a4b6-20d23d3bc47c" width="508" height="380"><img src="https:/ /events.vtools.ieee.org/vtools_ui/media/display/094061c3-a606-4726-8761-9f 504d095cc5" width="504" height="379">&nbsp\;</p>\n<p>&nbsp\;</p>\n<p><br>T he workshop began with an inaugural session\, marking the commencement of an insightful and technical journey into STA. Mr. Navneetha Krishnan intro duced the fundamentals of STA and its significance in VLSI circuit design. Participants were given an overview of the Cadence suite of tools used fo r STA\, including Tempus and Innovus. A live demonstration of these tools helped attendees familiarize themselves with the workflow and their functi onalities.</p>\n<p>One of the key hands-on activities of the first day was scripting an SDC (Synopsys Design Constraints) file. This exercise provid ed students with a fundamental understanding of how design constraints imp act timing analysis and overall circuit performance. The session began wit h an explanation of various SDC commands and their role in defining timing constraints. Participants learned to specify clock definitions\, input an d output delays\, false paths\, and multi-cycle paths using SDC syntax.</p >\n<p>To reinforce their understanding\, students engaged in practical scr ipting exercises where they defined constraints for a sample design. The s ession also included an introduction to scripting techniques using TCL (To ol Command Language)\, which is widely used in EDA tool automation. Studen ts explored how TCL scripting enhances efficiency by automating repetitive design constraints and modifications.<br>&nbsp\;<br>Additionally\, the se ssion emphasized best practices for writing SDC files\, ensuring compatibi lity with tools like Cadence Tempus and Innovus. By the end of the session \, participants had successfully created and modified SDC files\, gaining hands-on experience in constraint definition. Later\, they began working o n a counter program\, setting the foundation for detailed timing analysis and understanding its implications on setup and hold time constraints.</p> \n<p>&nbsp\;.</p>\n<p>Day 2: Deep Dive into STA Concepts and Practical Ana lysis</p>\n<p>The second day of the workshop commenced with a comprehensiv e presentation on the theoretical basics of STA. Topics such as slack\, sk ew\, rise time\, fall time\, critical path analysis\, setup and hold time violations\, and clock timing analysis were thoroughly explained. This ses sion provided participants with the fundamental understanding necessary fo r effective STA implementation.</p>\n<p>Following the presentation\, parti cipants engaged in a hands-on session focused on solving STA problems. The y analyzed the critical paths of the counter program\, identified timing v iolations\, and worked on resolving setup and hold time violations. Clock timing analysis was also performed\, allowing students to gain deeper insi ghts into optimizing design performance. The session was highly interactiv e\, with real-time problem-solving and discussions on various STA challeng es encountered in industry applications.</p>\n<p>The workshop concluded wi th an interactive Q&amp\;A session\, where students had the opportunity to clarify doubts and discuss advanced topics related to STA. The knowledge imparted over the two days provided participants with a strong foundation in STA\, equipping them with skills highly relevant to the VLSI industry.< /p>\n<p>To recognize the efforts and participation of attendees\, certific ates were distributed at the end of the event. IEEE VLSI SB extends its he artfelt gratitude to Mr. Navneetha Krishnan for his expert guidance and va luable insights. The event was a resounding success\, providing students w ith the necessary technical proficiency and hands-on experience in STA\, p reparing them for future challenges in VLSI design and development.<br>&nb sp\;<br>This workshop proved to be immensely beneficial to students\, help ing them bridge the gap between theoretical knowledge and industry practic es. The practical exposure to Cadence tools\, coupled with a deep understa nding of STA concepts\, has strengthened their technical foundation and en hanced their employability in the semiconductor industry. The skills acqui red during this workshop will play a crucial role in their careers\, enabl ing them to tackle real-world challenges in VLSI design with confidence an d proficiency.</p>\n<p class="MsoBodyText" style="margin-top: 1.6pt\;"><!- - [if gte vml 1]><o:wrapblock><v:shapetype\n id="_x0000_t75" coordsize="2 1600\,21600" o:spt="75" o:preferrelative="t"\n path="m@4@5l@4@11@9@11@9@5 xe" filled="f" stroked="f">\n <v:stroke joinstyle="miter"/>\n <v:formula s>\n <v:f eqn="if lineDrawn pixelLineWidth 0"/>\n <v:f eqn="sum @0 1 0 "/>\n <v:f eqn="sum 0 0 @1"/>\n <v:f eqn="prod @2 1 2"/>\n <v:f eqn= "prod @3 21600 pixelWidth"/>\n <v:f eqn="prod @3 21600 pixelHeight"/>\n <v:f eqn="sum @0 0 1"/>\n <v:f eqn="prod @6 1 2"/>\n <v:f eqn="prod @7 21600 pixelWidth"/>\n <v:f eqn="sum @8 21600 0"/>\n <v:f eqn="prod @7 21600 pixelHeight"/>\n <v:f eqn="sum @10 21600 0"/>\n </v:formulas>\ n <v:path o:extrusionok="f" gradientshapeok="t" o:connecttype="rect"/>\n <o:lock v:ext="edit" aspectratio="t"/>\n </v:shapetype><v:shape id="Image _x0020_5" o:spid="_x0000_s1027" type="#_x0000_t75"\n style='position:abso lute\;margin-left:186.7pt\;margin-top:14.35pt\;width:242.5pt\;\n height:2 73.55pt\;z-index:-15727104\;visibility:visible\;mso-wrap-style:square\;\n mso-wrap-distance-left:0\;mso-wrap-distance-top:0\;mso-wrap-distance-righ t:0\;\n mso-wrap-distance-bottom:0\;mso-position-horizontal:absolute\;\n mso-position-horizontal-relative:page\;mso-position-vertical:absolute\;\n mso-position-vertical-relative:text'>\n <v:imagedata src="file:///C:/Us ers/jalaj/AppData/Local/Temp/msohtmlclip1/01/clip_image001.jpg"\n o:titl e=""/>\n <o:lock v:ext="edit" aspectratio="f"/>\n <w:wrap type="topAndBo ttom" anchorx="page"/>\n </v:shape><v:shape id="Image_x0020_6" o:spid="_x0 000_s1026" type="#_x0000_t75"\n style='position:absolute\;margin-left:134 .05pt\;margin-top:299.25pt\;width:340.45pt\;\n height:236.4pt\;z-index:-1 5726592\;visibility:visible\;mso-wrap-style:square\;\n mso-wrap-distance- left:0\;mso-wrap-distance-top:0\;mso-wrap-distance-right:0\;\n mso-wrap-d istance-bottom:0\;mso-position-horizontal:absolute\;\n mso-position-horiz ontal-relative:page\;mso-position-vertical:absolute\;\n mso-position-vert ical-relative:text'>\n <v:imagedata src="file:///C:/Users/jalaj/AppData/L ocal/Temp/msohtmlclip1/01/clip_image002.jpg"\n o:title=""/>\n <o:lock v :ext="edit" aspectratio="f"/>\n <w:wrap type="topAndBottom" anchorx="page "/>\n </v:shape><![endif]--><!-- [if !vml]--></p>\n<p class="MsoBodyText" style="margin-top: 1.6pt\;"><!--[endif]--><!-- [if gte vml 1]></o:wrapbloc k><![endif]--><img src="https://events.vtools.ieee.org/vtools_ui/media/dis play/215ffc7d-936c-4c57-9823-41af5539e598" width="331" height="374"><img s rc="https://events.vtools.ieee.org/vtools_ui/media/display/995b27e7-5e9d-4 77e-95f4-9c36f84719ac" width="545" height="378"></p>\n<p class="MsoBodyTex t" style="margin-top: .3pt\;"><span lang="EN-US" style="font-size: 8.5pt\; mso-bidi-font-size: 11.5pt\;">&nbsp\;</span></p>\n<p class="MsoBodyText" style="line-height: 103%\; margin: 0cm 13.15pt .0001pt 18.0pt\;">&nbsp\;</ p> END:VEVENT END:VCALENDAR