BEGIN:VCALENDAR
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CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
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DTSTART:20380119T084407
TZOFFSETFROM:+0530
TZOFFSETTO:+0530
RRULE:FREQ=YEARLY;BYDAY=3TU;BYMONTH=1
TZNAME:+0530
END:DAYLIGHT
BEGIN:STANDARD
DTSTART:20060415T000000
TZOFFSETFROM:+0600
TZOFFSETTO:+0530
RRULE:FREQ=YEARLY;BYDAY=3SA;BYMONTH=4
TZNAME:+0530
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20250730T040322Z
UID:CF806EB0-D441-4BD6-B1D0-E4698AACF203
DTSTART;TZID=Asia/Colombo:20250201T083000
DTEND;TZID=Asia/Colombo:20250201T160000
DESCRIPTION:[]\n\nThe VLSI Workshop conducted by Synopsys successfully prov
 ided students with hands-on exposure to advanced Electronic Design Automat
 ion (EDA) tools\, bridging the gap between theoretical learning and practi
 cal applications in VLSI design and verification.\n\nThe workshop was effe
 ctively executed with a structured approach\, starting with an introductio
 n to modern semiconductor workflows and progressing to in-depth sessions o
 n industry-standard tools such as VC Spyglass for static verification\, VC
 S for functional verification\, and Design Compiler for logic synthesis. I
 nteractive demonstrations and guided explanations ensured participants cou
 ld directly relate tool usage to real-world design scenarios.\n\nThis init
 iative embodied IEEE’s mission of advancing technology for humanity by e
 mpowering students with relevant technical knowledge. It also promoted col
 laboration\, lifelong learning\, and professional growth\, aligning with I
 EEE’s commitment to developing future-ready engineers.\n\nThis impactful
  workshop set a strong foundation for students aspiring to excel in semico
 nductor design and verification.\n\nImpact:\n\n-\nEnhanced participants’
  understanding of EDA toolchains and their relevance in the semiconductor 
 industry.\n\n-\nInspired undergraduates to explore career opportunities an
 d research in VLSI and digital design domains.\n\n-\nStrengthened collabor
 ation between academia and industry by enabling direct interaction with ex
 perts.\n\n[][][][][][]\n\nCo-sponsored by: Synopsys Lanka (Pvt) Ltd\n\nAge
 nda: \n-\nWelcome Speech by Dr. Isuru Dassanayake\n08:30 AM – 09:00 AM\n
 \n-\nSession 1\n09:00 AM – 10:30 AM\n\n-\nRefreshments\n10:30 AM – 11:
 00 AM\n\n-\nSession 1 – Continuation\n11:00 AM – 12:00 PM\n\n-\nLunch 
 Break\n12:00 PM – 01:00 PM\n\n-\nSession 2\n01:00 PM – 03:00 PM\n\n-\n
 Refreshments\n03:00 PM – 03:30 PM\n\n-\nSession 2 – Continuation\n03:3
 0 PM – 04:00 PM\n\nBldg: Computer Lab 02\, Faculty of Engineering\, Univ
 ersity of Peradeniya\, Peradeniya\, Sri Lanka\, Sri Lanka\, 20400
LOCATION:Bldg: Computer Lab 02\, Faculty of Engineering\, University of Per
 adeniya\, Peradeniya\, Sri Lanka\, Sri Lanka\, 20400
ORGANIZER:ieeepdn@gmail.com
SEQUENCE:482
SUMMARY:VLSI Workshop 1 by Synopsys
URL;VALUE=URI:https://events.vtools.ieee.org/m/484828
X-ALT-DESC:Description: &lt;br /&gt;&lt;p data-start=&quot;112&quot; data-end=&quot;379&quot;&gt;&lt;img style
 =&quot;float: left\;&quot; src=&quot;https://events.vtools.ieee.org/vtools_ui/media/displ
 ay/b5714d98-4bf8-49f5-9a6c-204fb2a82a9e&quot; alt=&quot;&quot; width=&quot;259&quot; height=&quot;367&quot;&gt;&lt;
 /p&gt;\n&lt;p style=&quot;padding-left: 320px\; text-align: justify\;&quot; data-start=&quot;11
 2&quot; data-end=&quot;379&quot;&gt;&amp;nbsp\; The &lt;strong data-start=&quot;116&quot; data-end=&quot;155&quot;&gt;VLSI
  Workshop conducted by Synopsys&lt;/strong&gt; successfully provided students wi
 th hands-on exposure to&amp;nbsp\; &amp;nbsp\;advanced &lt;strong data-start=&quot;222&quot; da
 ta-end=&quot;260&quot;&gt;Electronic Design Automation (EDA)&lt;/strong&gt; tools\, bridging 
 the gap between theoretical learning and&amp;nbsp\; &amp;nbsp\;practical applicati
 ons in &lt;strong data-start=&quot;344&quot; data-end=&quot;376&quot;&gt;VLSI design and verificatio
 n&lt;/strong&gt;.&lt;/p&gt;\n&lt;p style=&quot;padding-left: 320px\; text-align: justify\;&quot; da
 ta-start=&quot;112&quot; data-end=&quot;379&quot;&gt;&amp;nbsp\; The workshop was effectively execute
 d with a structured approach\, starting with an introduction to&amp;nbsp\; &amp;nb
 sp\;modern semiconductor workflows and progressing to in-depth sessions on
  industry-standard tools such as&amp;nbsp\; &amp;nbsp\;&lt;strong data-start=&quot;617&quot; da
 ta-end=&quot;632&quot;&gt;VC Spyglass&lt;/strong&gt; for static verification\, &lt;strong data-s
 tart=&quot;658&quot; data-end=&quot;665&quot;&gt;VCS&lt;/strong&gt; for functional verification\, and &lt;
 strong data-start=&quot;699&quot; data-end=&quot;718&quot;&gt;Design Compiler&lt;/strong&gt; for logic 
 synthesis.&amp;nbsp\; &amp;nbsp\;Interactive demonstrations and guided explanation
 s ensured participants could directly relate tool usage to&amp;nbsp\; &amp;nbsp\;r
 eal-world design scenarios.&lt;/p&gt;\n&lt;p style=&quot;padding-left: 320px\; text-alig
 n: justify\;&quot; data-start=&quot;1228&quot; data-end=&quot;1537&quot;&gt;This initiative embodied &lt;
 strong data-start=&quot;1272&quot; data-end=&quot;1327&quot;&gt;IEEE&amp;rsquo\;s mission of advancin
 g technology for humanity&lt;/strong&gt; by empowering students with relevant te
 chnical knowledge. It also promoted &lt;strong data-start=&quot;1403&quot; data-end=&quot;14
 64&quot;&gt;collaboration\, lifelong learning\, and professional growth&lt;/strong&gt;\,
  aligning with IEEE&amp;rsquo\;s commitment to developing future-ready enginee
 rs.&lt;/p&gt;\n&lt;p style=&quot;padding-left: 320px\; text-align: justify\;&quot; data-start
 =&quot;1539&quot; data-end=&quot;1665&quot;&gt;This impactful workshop set a strong foundation fo
 r students aspiring to excel in &lt;strong data-start=&quot;1621&quot; data-end=&quot;1662&quot;&gt;
 semiconductor design and verification&lt;/strong&gt;.&lt;/p&gt;\n&lt;p style=&quot;text-align:
  justify\;&quot; data-start=&quot;112&quot; data-end=&quot;379&quot;&gt;&amp;nbsp\;&lt;/p&gt;\n&lt;p data-start=&quot;88
 0&quot; data-end=&quot;893&quot;&gt;&lt;strong data-start=&quot;880&quot; data-end=&quot;891&quot;&gt;&amp;nbsp\; &lt;/strong
 &gt;&lt;/p&gt;\n&lt;p data-start=&quot;880&quot; data-end=&quot;893&quot;&gt;&amp;nbsp\;&lt;/p&gt;\n&lt;p data-start=&quot;880&quot;
  data-end=&quot;893&quot;&gt;&amp;nbsp\;&lt;/p&gt;\n&lt;p data-start=&quot;880&quot; data-end=&quot;893&quot;&gt;&amp;nbsp\;&lt;/p
 &gt;\n&lt;p data-start=&quot;880&quot; data-end=&quot;893&quot;&gt;&lt;strong data-start=&quot;880&quot; data-end=&quot;8
 91&quot;&gt;Impact:&lt;/strong&gt;&lt;/p&gt;\n&lt;ul data-start=&quot;894&quot; data-end=&quot;1226&quot;&gt;\n&lt;li data-
 start=&quot;894&quot; data-end=&quot;1007&quot;&gt;\n&lt;p data-start=&quot;896&quot; data-end=&quot;1007&quot;&gt;Enhanced
  participants&amp;rsquo\; understanding of &lt;strong data-start=&quot;936&quot; data-end=&quot;
 954&quot;&gt;EDA toolchains&lt;/strong&gt; and their relevance in the semiconductor indu
 stry.&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-start=&quot;1008&quot; data-end=&quot;1120&quot;&gt;\n&lt;p data-start=&quot;1
 010&quot; data-end=&quot;1120&quot;&gt;Inspired undergraduates to explore career opportuniti
 es and research in &lt;strong data-start=&quot;1082&quot; data-end=&quot;1109&quot;&gt;VLSI and digi
 tal design&lt;/strong&gt; domains.&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-start=&quot;1121&quot; data-end=&quot;1
 226&quot;&gt;\n&lt;p data-start=&quot;1123&quot; data-end=&quot;1226&quot;&gt;Strengthened collaboration bet
 ween academia and industry by enabling direct interaction with experts.&lt;/p
 &gt;\n&lt;/li&gt;\n&lt;/ul&gt;\n&lt;p data-start=&quot;1539&quot; data-end=&quot;1665&quot;&gt;&lt;img src=&quot;https://ev
 ents.vtools.ieee.org/vtools_ui/media/display/f2f45539-1205-408a-80b8-6af6d
 6974c76&quot; alt=&quot;&quot; width=&quot;376&quot; height=&quot;283&quot;&gt;&lt;img src=&quot;https://events.vtools.i
 eee.org/vtools_ui/media/display/fe2f2a16-6715-4667-ac82-abb56ea7457f&quot; alt=
 &quot;&quot; width=&quot;210&quot; height=&quot;280&quot;&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vtool
 s_ui/media/display/a05cf8a6-859b-4eb5-aca1-6b7252c26c53&quot; alt=&quot;&quot; width=&quot;256
 &quot; height=&quot;276&quot;&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vtools_ui/media/di
 splay/0d4c11f3-269d-45e6-98ab-c1d6c26cc76e&quot; alt=&quot;&quot; width=&quot;159&quot; height=&quot;275
 &quot;&gt;&lt;img src=&quot;https://events.vtools.ieee.org/vtools_ui/media/display/cc25139
 3-4618-48fb-8c33-7fcf5bbf0833&quot; alt=&quot;&quot; width=&quot;162&quot; height=&quot;280&quot;&gt;&lt;img src=&quot;h
 ttps://events.vtools.ieee.org/vtools_ui/media/display/6af34be7-bfdf-46a6-9
 4c3-ff2b46c6263a&quot; alt=&quot;&quot; width=&quot;175&quot; height=&quot;275&quot;&gt;&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: 
 &lt;br /&gt;&lt;p&gt;&amp;nbsp\;&lt;/p&gt;\n&lt;ul&gt;\n&lt;li data-start=&quot;94&quot; data-end=&quot;169&quot;&gt;\n&lt;p data-s
 tart=&quot;97&quot; data-end=&quot;169&quot;&gt;&lt;strong data-start=&quot;97&quot; data-end=&quot;140&quot;&gt;Welcome Sp
 eech by Dr. Isuru Dassanayake&lt;/strong&gt;&lt;br data-start=&quot;140&quot; data-end=&quot;143&quot;&gt;
 &lt;em data-start=&quot;146&quot; data-end=&quot;167&quot;&gt;08:30 AM &amp;ndash\; 09:00 AM&lt;/em&gt;&lt;/p&gt;\n&lt;
 /li&gt;\n&lt;li data-start=&quot;171&quot; data-end=&quot;216&quot;&gt;\n&lt;p data-start=&quot;174&quot; data-end=&quot;
 216&quot;&gt;&lt;strong data-start=&quot;174&quot; data-end=&quot;187&quot;&gt;Session 1&lt;/strong&gt;&lt;br data-st
 art=&quot;187&quot; data-end=&quot;190&quot;&gt;&lt;em data-start=&quot;193&quot; data-end=&quot;214&quot;&gt;09:00 AM &amp;nda
 sh\; 10:30 AM&lt;/em&gt;&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-start=&quot;218&quot; data-end=&quot;266&quot;&gt;\n&lt;p da
 ta-start=&quot;221&quot; data-end=&quot;266&quot;&gt;&lt;strong data-start=&quot;221&quot; data-end=&quot;237&quot;&gt;Refr
 eshments&lt;/strong&gt;&lt;br data-start=&quot;237&quot; data-end=&quot;240&quot;&gt;&lt;em data-start=&quot;243&quot; 
 data-end=&quot;264&quot;&gt;10:30 AM &amp;ndash\; 11:00 AM&lt;/em&gt;&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-start=
 &quot;268&quot; data-end=&quot;328&quot;&gt;\n&lt;p data-start=&quot;271&quot; data-end=&quot;328&quot;&gt;&lt;strong data-sta
 rt=&quot;271&quot; data-end=&quot;299&quot;&gt;Session 1 &amp;ndash\; Continuation&lt;/strong&gt;&lt;br data-s
 tart=&quot;299&quot; data-end=&quot;302&quot;&gt;&lt;em data-start=&quot;305&quot; data-end=&quot;326&quot;&gt;11:00 AM &amp;nd
 ash\; 12:00 PM&lt;/em&gt;&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-start=&quot;330&quot; data-end=&quot;377&quot;&gt;\n&lt;p d
 ata-start=&quot;333&quot; data-end=&quot;377&quot;&gt;&lt;strong data-start=&quot;333&quot; data-end=&quot;348&quot;&gt;Lun
 ch Break&lt;/strong&gt;&lt;br data-start=&quot;348&quot; data-end=&quot;351&quot;&gt;&lt;em data-start=&quot;354&quot; 
 data-end=&quot;375&quot;&gt;12:00 PM &amp;ndash\; 01:00 PM&lt;/em&gt;&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-start=
 &quot;379&quot; data-end=&quot;424&quot;&gt;\n&lt;p data-start=&quot;382&quot; data-end=&quot;424&quot;&gt;&lt;strong data-sta
 rt=&quot;382&quot; data-end=&quot;395&quot;&gt;Session 2&lt;/strong&gt;&lt;br data-start=&quot;395&quot; data-end=&quot;3
 98&quot;&gt;&lt;em data-start=&quot;401&quot; data-end=&quot;422&quot;&gt;01:00 PM &amp;ndash\; 03:00 PM&lt;/em&gt;&lt;/p
 &gt;\n&lt;/li&gt;\n&lt;li data-start=&quot;426&quot; data-end=&quot;474&quot;&gt;\n&lt;p data-start=&quot;429&quot; data-e
 nd=&quot;474&quot;&gt;&lt;strong data-start=&quot;429&quot; data-end=&quot;445&quot;&gt;Refreshments&lt;/strong&gt;&lt;br 
 data-start=&quot;445&quot; data-end=&quot;448&quot;&gt;&lt;em data-start=&quot;451&quot; data-end=&quot;472&quot;&gt;03:00 
 PM &amp;ndash\; 03:30 PM&lt;/em&gt;&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-start=&quot;476&quot; data-end=&quot;536&quot;&gt;
 \n&lt;p data-start=&quot;479&quot; data-end=&quot;536&quot;&gt;&lt;strong data-start=&quot;479&quot; data-end=&quot;50
 7&quot;&gt;Session 2 &amp;ndash\; Continuation&lt;/strong&gt;&lt;br data-start=&quot;507&quot; data-end=&quot;
 510&quot;&gt;&lt;em data-start=&quot;513&quot; data-end=&quot;534&quot;&gt;03:30 PM &amp;ndash\; 04:00 PM&lt;/em&gt;&lt;/
 p&gt;\n&lt;/li&gt;\n&lt;/ul&gt;
END:VEVENT
END:VCALENDAR