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DTSTAMP:20250523T203554Z
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DTSTART;TZID=America/Chicago:20250520T110000
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DESCRIPTION:Speaker:\n\nAndrea Grimaldi\n\nAffiliation:\n\nPolytechnic Univ
 ersity of Bari\, Italy\n\nTitle:\n\nProbabilistic Ising Machines: From Alg
 orithms to Hardware\n\nDate/Time:\n\nTuesday- May 20\, 2025\n\n11:00 AM - 
 12:00 PM\n\nZoom link\n\n[https://argonne.zoomgov.com/j/1611401597?pwd=mph
 qouuBv8a17t0p5womEh4oNq4uQC.1](https://urldefense.us/v3/__https://argonne.
 zoomgov.com/j/1611401597?pwd=mphqouuBv8a17t0p5womEh4oNq4uQC.1__\;!!G_uCfsc
 f7eWS!a2fm6yALkdLT5ez5z6zkj0YTh3fyOaM5unaXDT2-gw74tW5gRUxRWs4LHTNJo2-9gFh1
 amfjuXXZz2hEjMqjWCDiZdfO-aw$)\n\nAbstract:\n\nIsing machines are an unconv
 entional computing paradigm that consists in determining the solution to h
 ard computational problems by finding the energy minimum of an Ising model
 . Out of the possible implementations\, probabilistic Ising machine rely o
 n the p-bit\, a bistable\, tunable\, stochastic unit [1] that can be easil
 y implemented by physical systems like spintronic diodes [2]. To maximize 
 the performance of such a system\, it is necessary to work on three levels
 : the encoding\, the energy minimization schedule\, and the implementation
 .\n\nThe implementation of the Ising machine is what establishes the worki
 ng speed\, and thus the performance\, of the system. Moreover\, different 
 hardware may impose limitations that also affect the compatible encodings 
 and energy minimization schedules. Field-programmable gate arrays\, for in
 stance\, allow for highly parallelizable computation\, but require sparse 
 graph topologies [3]. One of the technologies with the most potential for 
 Ising machines is spintronics. Devices like magnetic tunnel junctions are 
 intrinsically compatible with implementing an Ising spin in several ways. 
 The parallel and anti-parallel state may encode the up and down state of t
 he p-bit [5]\, or the phase of an oscillating magnetization of a spin-torq
 ue nano oscillator can be discretized using injection-locking to obtain th
 e spin of an oscillatory Ising machine [5]. These systems are incredibly c
 ompact and energy efficient\, on top of being characterized by high workin
 g speed and CMOS compatibility\, making them excellent candidates for futu
 re applications geared towards the solution of computational problems in d
 edicated hardware.\n\nCo-sponsored by: IEEE Chicago\, IEEE NTC Young Profe
 ssionals\n\nVirtual: https://events.vtools.ieee.org/m/485917
LOCATION:Virtual: https://events.vtools.ieee.org/m/485917
ORGANIZER:yili@anl.gov
SEQUENCE:12
SUMMARY:(May 20\, 2025) Probabilistic Ising Machines: From Algorithms to Ha
 rdware
URL;VALUE=URI:https://events.vtools.ieee.org/m/485917
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;&lt;strong data-olk-copy-source=&quot;MessageBody&quot;
 &gt;Speaker:&amp;nbsp\; &amp;nbsp\;&lt;/strong&gt;&lt;/p&gt;\n&lt;p&gt;&lt;span class=&quot;markla9j76utx&quot; data
 -markjs=&quot;true&quot; data-ogac=&quot;&quot; data-ogab=&quot;&quot; data-ogsc=&quot;&quot; data-ogsb=&quot;&quot;&gt;Andrea&lt;
 /span&gt; Grimaldi&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;Affiliation:&amp;nbsp\; &amp;nbsp\;&lt;/strong&gt;&lt;/p&gt;\n
 &lt;p&gt;Polytechnic University of Bari\, Italy&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;Title:&amp;nbsp\;&lt;/s
 trong&gt;&lt;/p&gt;\n&lt;p&gt;Probabilistic Ising Machines: From Algorithms to Hardware&lt;/
 p&gt;\n&lt;p&gt;&lt;strong&gt;Date/Time:&amp;nbsp\; &amp;nbsp\; &amp;nbsp\;&lt;/strong&gt;&lt;/p&gt;\n&lt;p&gt;Tuesday-
  May 20\, 2025&lt;/p&gt;\n&lt;p&gt;11:00 AM -&amp;nbsp\; 12:00 PM&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;Zoom lin
 k&lt;/strong&gt;&lt;/p&gt;\n&lt;p&gt;&lt;a id=&quot;LPlnk673179&quot; title=&quot;https://urldefense.us/v3/__h
 ttps://argonne.zoomgov.com/j/1611401597?pwd=mphqouuBv8a17t0p5womEh4oNq4uQC
 .1__\;!!G_uCfscf7eWS!a2fm6yALkdLT5ez5z6zkj0YTh3fyOaM5unaXDT2-gw74tW5gRUxRW
 s4LHTNJo2-9gFh1amfjuXXZz2hEjMqjWCDiZdfO-aw$&quot; href=&quot;https://urldefense.us/v
 3/__https://argonne.zoomgov.com/j/1611401597?pwd=mphqouuBv8a17t0p5womEh4oN
 q4uQC.1__\;!!G_uCfscf7eWS!a2fm6yALkdLT5ez5z6zkj0YTh3fyOaM5unaXDT2-gw74tW5g
 RUxRWs4LHTNJo2-9gFh1amfjuXXZz2hEjMqjWCDiZdfO-aw$&quot; target=&quot;_blank&quot; rel=&quot;noo
 pener noreferrer&quot; data-auth=&quot;NotApplicable&quot; data-linkindex=&quot;0&quot; data-olk-co
 py-source=&quot;MessageBody&quot;&gt;https://argonne.zoomgov.com/j/1611401597?pwd=mphqo
 uuBv8a17t0p5womEh4oNq4uQC.1&lt;/a&gt;&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;Abstract:&lt;/strong&gt;&lt;/p&gt;\n&lt;p
 &gt;Ising machines are an unconventional computing paradigm that consists in 
 determining the solution to hard computational problems by finding the ene
 rgy minimum of an Ising model. Out of the possible implementations\, proba
 bilistic Ising machine rely on the p-bit\, a bistable\, tunable\, stochast
 ic unit [1] that can be easily implemented by physical systems like spintr
 onic diodes [2]. To maximize the performance of such a system\, it is nece
 ssary to work on three levels: the encoding\, the energy minimization sche
 dule\, and the implementation.&lt;/p&gt;\n&lt;p&gt;The implementation of the Ising mac
 hine is what establishes the working speed\, and thus the performance\, of
  the system. Moreover\, different hardware may impose limitations that als
 o affect the compatible encodings and energy minimization schedules. Field
 -programmable gate arrays\, for instance\, allow for highly parallelizable
  computation\, but require sparse graph topologies [3]. One of the technol
 ogies with the most potential for Ising machines is spintronics. Devices l
 ike magnetic tunnel junctions are intrinsically compatible with implementi
 ng an Ising spin in several ways. The parallel and anti-parallel state may
  encode the up and down state of the p-bit [5]\, or the phase of an oscill
 ating magnetization of a spin-torque nano oscillator can be discretized us
 ing injection-locking to obtain the spin of an oscillatory Ising machine [
 5]. These systems are incredibly compact and energy efficient\, on top of 
 being characterized by high working speed and CMOS compatibility\, making 
 them excellent candidates for future applications geared towards the solut
 ion of computational problems in dedicated hardware.&lt;/p&gt;\n&lt;p&gt;&lt;!-- [if supp
 ortFields]&gt;&lt;span style=&#39;font-size:12.0pt\;line-height:115%\;\nfont-family:
 &quot;Aptos&quot;\,&quot;sans-serif&quot;\;mso-ascii-theme-font:minor-latin\;mso-fareast-font-
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