BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:America/New_York
BEGIN:DAYLIGHT
DTSTART:20250309T030000
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3
TZNAME:EDT
END:DAYLIGHT
BEGIN:STANDARD
DTSTART:20251102T010000
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11
TZNAME:EST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20250624T144635Z
UID:84CA7EC6-D295-40FF-ACD7-A00039EFC38E
DTSTART;TZID=America/New_York:20250623T170000
DTEND;TZID=America/New_York:20250623T193000
DESCRIPTION:The increase in data rates and processing speeds driven by AI a
 nd next generation device complexity\, require more precise filtering\, im
 proved signals\, and power with less noise. This discussion will focus on 
 the newest studies showing how using some ultra-thin and high Dk laminates
  in PCBs will improve the EMC\, SI and PI. It also shows benefits to space
  utilization\, and stack-up thicknesses.\n\nCo-sponsored by: Intertek USA\
 n\nSpeaker(s): Bob\, John\n\nAgenda: \nAgenda:\n\n5:00 pm Registration/che
 ck-in\, complimentary dinner and refreshments\n\n6:00 pm Welcome from Inte
 rtek and IEEE EMC-S Boston Chapter\n\n6:10 pm “The Impact on EMC\, SI\, 
 and PI When Using Ultra-Thin Laminates in PCBs” by Bob Carter and John R
 anieri\, Oak-Mitsui Technologies\n\n7:00 pm Q&amp;A – Closing Comments\n\n7:
 30 pm Adjourn\n\nIntertek USA\, 70 Codman Hill Rd.\,  Boxborough\, Massach
 usetts\, United States\, 01719
LOCATION:Intertek USA\, 70 Codman Hill Rd.\,  Boxborough\, Massachusetts\, 
 United States\, 01719
ORGANIZER:shusterm2@gmail.com
SEQUENCE:32
SUMMARY:The impact on EMC\, SI\, and PI when using Ultra-Thin Laminates in 
 PCBs
URL;VALUE=URI:https://events.vtools.ieee.org/m/486199
X-ALT-DESC:Description: &lt;br /&gt;&lt;p class=&quot;MsoNormal&quot;&gt;The increase in data rat
 es and processing speeds driven by AI and next generation device complexit
 y\, require more precise filtering\, improved signals\, and power with les
 s noise. This discussion will focus on the newest studies showing how usin
 g some ultra-thin and high Dk laminates in PCBs will improve the EMC\, SI 
 and PI.&amp;nbsp\; It also shows benefits to space utilization\, and stack-up 
 thicknesses.&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;br /&gt;&lt;p class=&quot;MsoNormal&quot;&gt;&lt;strong&gt;&lt;u&gt;
 &lt;span style=&quot;font-size: 14.0pt\; line-height: 115%\;&quot;&gt;Agenda&lt;/span&gt;&lt;/u&gt;&lt;/s
 trong&gt;&lt;strong&gt;&lt;span style=&quot;font-size: 14.0pt\; line-height: 115%\;&quot;&gt;:&lt;/spa
 n&gt;&lt;/strong&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot;&gt;&lt;span style=&quot;font-size: 11.0pt\; lin
 e-height: 115%\; font-family: &#39;Calibri&#39;\,sans-serif\; color: #333333\;&quot;&gt;5:
 00 pm Registration/check-in\, complimentary dinner and refreshments &lt;/span
 &gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNormal&quot;&gt;&lt;span style=&quot;font-size: 11.0pt\; line-height: 
 115%\; font-family: &#39;Calibri&#39;\,sans-serif\; color: #333333\;&quot;&gt;6:00 pm Welc
 ome from Intertek and IEEE EMC-S Boston Chapter&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoN
 ormal&quot;&gt;&lt;span style=&quot;font-size: 11.0pt\; line-height: 115%\; font-family: &#39;
 Calibri&#39;\,sans-serif\; color: #333333\;&quot;&gt;6:10 pm &amp;ldquo\;The Impact on EMC
 \, SI\, and PI When Using Ultra-Thin Laminates in PCBs&amp;rdquo\; by Bob Cart
 er and John Ranieri\, Oak-Mitsui Technologies&lt;/span&gt;&lt;/p&gt;\n&lt;p class=&quot;MsoNor
 mal&quot;&gt;&lt;span style=&quot;font-size: 11.0pt\; font-family: &#39;Calibri&#39;\,sans-serif\;
  color: #333333\;&quot;&gt;7:00 pm Q&amp;amp\;A &amp;ndash\; Closing Comments&lt;/span&gt;&lt;/p&gt;\n
 &lt;p class=&quot;MsoNormal&quot;&gt;&lt;span style=&quot;font-size: 11.0pt\; line-height: 115%\; 
 font-family: &#39;Calibri&#39;\,sans-serif\; color: #333333\;&quot;&gt;7:30 pm Adjourn&amp;nbs
 p\;&amp;nbsp\;&lt;/span&gt;&lt;/p&gt;
END:VEVENT
END:VCALENDAR