BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:America/New_York
BEGIN:DAYLIGHT
DTSTART:20250309T030000
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3
TZNAME:EDT
END:DAYLIGHT
BEGIN:STANDARD
DTSTART:20251102T010000
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11
TZNAME:EST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260305T040517Z
UID:EA1D310F-37BA-4AE5-9E4B-87C434B61E3B
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DTEND;TZID=America/New_York:20250703T131500
DESCRIPTION:Analog/RF IC design has been traditionally considered an art 
 – sometimes even a “black art” – because\, contrary to digital IC 
 design\, analog/RF design combines complexity\, non-linearity\, conflictin
 g design objectives and limited automation in EDA tooling. Analog/RF IC de
 signers rely on a blend of technical expertise\, intuition\, accumulated e
 xperience\, and creativity to meet the demanding targets of modern applica
 tions like high operating frequencies\, low power\, miniaturization\, and 
 shrinking design cycles.\n\nIn this webinar you will learn about the revol
 utionary AI-driven electromagnetic-aware methodology that automates the op
 timization of the floor plan of analog and RF physical layouts. Join us to
  discover how Ansys AI solutions can add structure to the “madness” of
  analog/RF design.\n\nWhat attendees will learn\n\n- How the Ansys AI-driv
 en electromagnetic-aware methodology blends with your existing custom IC d
 esign methodology and design flow\n- How to define goals and constraints t
 o identify the global optimum instead of settling for locally optimal solu
 tions\n- How the Ansys AI-driven optimization methodology will help you sh
 ave off several days or weeks from your design cycle\n\nWho should attend\
 n\n- Custom (analog/RF/high-speed) IC designers\n- Signal Integrity engine
 ers involved in the design and sign-off of high-speed buses on silicon int
 erposers\n\nSpeaker(s): Kelly Damalou\, \n\nVirtual: https://events.vtools
 .ieee.org/m/486599
LOCATION:Virtual: https://events.vtools.ieee.org/m/486599
ORGANIZER:aabdella@ieee.org
SEQUENCE:43
SUMMARY:AI-Driven Physics-based Analog Design Optimization
URL;VALUE=URI:https://events.vtools.ieee.org/m/486599
X-ALT-DESC:Description: <br /><p><img style="display: block\; margin-left: 
 auto\; margin-right: auto\;" src="https://events.vtools.ieee.org/vtools_ui
 /media/display/f6554e76-88ed-4835-87d6-32e94d0b68ba" width="766" height="4
 40"></p>\n<p>Analog/RF IC design has been traditionally considered an art 
 &ndash\; sometimes even a &ldquo\;black art&rdquo\; &ndash\; because\, con
 trary to digital IC design\, analog/RF design combines complexity\, non-li
 nearity\, conflicting design objectives and limited automation in EDA tool
 ing. Analog/RF IC designers rely on a blend of technical expertise\, intui
 tion\, accumulated experience\, and creativity to meet the demanding targe
 ts of modern applications like high operating frequencies\, low power\, mi
 niaturization\, and shrinking design cycles.</p>\n<p>In this webinar you w
 ill learn about the revolutionary AI-driven electromagnetic-aware methodol
 ogy that automates the optimization of the floor plan of analog and RF phy
 sical layouts. Join us to discover how Ansys AI solutions can add structur
 e to the &ldquo\;madness&rdquo\; of analog/RF design.</p>\n<h2>What attend
 ees will learn</h2>\n<ul>\n<li>How the Ansys AI-driven electromagnetic-awa
 re methodology blends with your existing custom IC design methodology and 
 design flow</li>\n<li>How to define goals and constraints to identify the 
 global optimum instead of settling for locally optimal solutions</li>\n<li
 >How the Ansys AI-driven optimization methodology will help you shave off 
 several days or weeks from your design cycle</li>\n</ul>\n<h2>Who should a
 ttend</h2>\n<ul>\n<li>Custom (analog/RF/high-speed) IC designers</li>\n<li
 >Signal Integrity engineers involved in the design and sign-off of high-sp
 eed buses on silicon interposers</li>\n</ul>
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