BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20250309T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20251102T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250701T233258Z UID:D6BCF2B4-5FB1-41ED-AB7E-388088379917 DTSTART;TZID=America/Los_Angeles:20250627T113000 DTEND;TZID=America/Los_Angeles:20250627T130000 DESCRIPTION:As Moore’s Law is slowing down and eventually approaching an end for conventional CMOS\, new platforms for producing circuit-level inno vation are desired. At the same time\, it is not desirable to throw away t he existing Si-CMOS infrastructure to start new. This talk presents an ove rview of the 10-year research program\, which is a “vertical” innovati ve platform by “inserting” III-V layers into a conventional Si-CMOS fo undry process. The talk also presents a unified compact model for generic GaN/InGaAs-based HEMTs in the context of the hybrid III-V + CMOS technolog y developed for future heterogeneous integrated circuits. The developed mo del has been implemented in a hybrid III-V/CMOS foundry PDK for designing heterogeneous circuits in III-V/Si monolithically co-integrated technology .\n\nWhen: Friday\, June 27th\, 2025 – 11:30AM to 1PM (PDT)\n\n11:30AM - 12PM: Networking / Pizza\n12PM-12:45PM: Lecture\n12:45PM-12:55PM: Q&A\n1P M Adjourn\n\nBio:\n\nDr. Xing Zhou obtained his B.E. degree in electrical engineering from Tsinghua University in 1983\, M.S. and Ph.D. degrees in e lectrical engineering from the University of Rochester in 1987 and 1990\, respectively. He has been with the School of Electrical and Electronic Eng ineering\, Nanyang Technological University (NTU)\, Singapore from 1992 to 2024. His past research interests include Monte Carlo simulation of photo carrier transport and ultrafast phenomena as well as mixed-mode circuit si mulation and CAD tool development. His research at NTU mainly focuses on n anoscale CMOS compact model development. His research group has been devel oping a unified core model for nanoscale bulk\, SOI\, double-gate\, nanowi re CMOS\, as well as III-V HEMTs. He has given more than 150 IEEE EDS dist inguished lectures and invited talks at various universities as well as in dustry and research institutions. Dr. Zhou was the founding chair for the Workshop on Compact Modeling (WCM) in association with the NSTI Nanotechno logy Conference (2002–2018). He was an editor for the IEEE Electron Devi ce Letters (2007–2016)\, a guest Editor-in-Chief for the special issue o f the IEEE Transactions on Electron Devices (Feb. 2014) on compact modelin g of emerging devices\, and a member of the Modeling & Simulation subcommi ttee for IEDM (2016\, 2017). He was an Elected Member-at-Large of EDS Boar d of Governors (2004–2009\; 2011–2016) and served as Vice-President fo r Regions/Chapters (2013–2015). He has been an EDS Distinguished Lecture r since 2000. He is a Life Senior Member of the IEEE and currently serves as chair for the RS/EPS/EDS Singapore Joint Chapter.\n\nSunnyvale\, Califo rnia\, United States\, Virtual: https://events.vtools.ieee.org/m/487617 LOCATION:Sunnyvale\, California\, United States\, Virtual: https://events.v tools.ieee.org/m/487617 ORGANIZER:ieeescveds@gmail.com SEQUENCE:19 SUMMARY:Monolithic Co-integration of III-V Materials into Foundry Si-CMOS i n a Single Chip for Novel Integrated Circuits URL;VALUE=URI:https://events.vtools.ieee.org/m/487617 X-ALT-DESC:Description: <br /><p class="MsoNormal">As Moore&rsquo\;s Law is slowing down and eventually approaching an end for conventional CMOS\, ne w platforms for producing circuit-level innovation are desired. &nbsp\;At the same time\, it is not desirable to throw away the existing Si-CMOS inf rastructure to start new. &nbsp\;This talk presents an overview of the 10- year research program\, which is a &ldquo\;vertical&rdquo\; innovative pla tform by &ldquo\;inserting&rdquo\; III-V layers into a conventional Si-CMO S foundry process. &nbsp\;The talk also presents a unified compact model f or generic GaN/InGaAs-based HEMTs in the context of the hybrid III-V + CMO S technology developed for future heterogeneous integrated circuits. &nbsp \;The developed model has been implemented in a hybrid III-V/CMOS foundry PDK for designing heterogeneous circuits in III-V/Si monolithically co-int egrated technology.</p>\n<p class="MsoNormal">When: Friday\, June 27th\, 2 025 &ndash\; 11:30AM to 1PM (PDT)&nbsp\;<br><br>11:30AM - 12PM: Networking / Pizza <br>12PM-12:45PM: Lecture <br>12:45PM-12:55PM: Q&amp\;A <br>1PM A djourn</p>\n<p class="MsoNormal">Bio:</p>\n<p>Dr. Xing Zhou obtained his B .E. degree in electrical engineering from Tsinghua University in 1983\, M. S. and Ph.D. degrees in electrical engineering from the University of Roch ester in 1987 and 1990\, respectively. &nbsp\;He has been with the School of Electrical and Electronic Engineering\, Nanyang Technological Universit y (NTU)\, Singapore from 1992 to 2024. &nbsp\;His past research interests include Monte Carlo simulation of photocarrier transport and ultrafast phe nomena as well as mixed-mode circuit simulation and CAD tool development. &nbsp\;His research at NTU mainly focuses on nanoscale CMOS compact model development. &nbsp\;His research group has been developing a unified core model for nanoscale bulk\, SOI\, double-gate\, nanowire CMOS\, as well as III-V HEMTs. &nbsp\;He has given more than 150 IEEE EDS distinguished lect ures and invited talks at various universities as well as industry and res earch institutions. &nbsp\;Dr. Zhou was the founding chair for the Worksho p on Compact Modeling (WCM) in association with the NSTI Nanotechnology Co nference (2002&ndash\;2018). &nbsp\;He was an editor for the IEEE Electron Device Letters (2007&ndash\;2016)\, a guest Editor-in-Chief for the speci al issue of the IEEE Transactions on Electron Devices (Feb. 2014) on compa ct modeling of emerging devices\, and a member of the Modeling &amp\; Simu lation subcommittee for IEDM (2016\, 2017). &nbsp\;He was an Elected Membe r-at-Large of EDS Board of Governors (2004&ndash\;2009\; 2011&ndash\;2016) and served as Vice-President for Regions/Chapters (2013&ndash\;2015). &nb sp\;He has been an EDS Distinguished Lecturer since 2000. &nbsp\;He is a L ife Senior Member of the IEEE and currently serves as chair for the RS/EPS /EDS Singapore Joint Chapter.</p> END:VEVENT END:VCALENDAR