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TZID:Asia/Dhaka
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DTSTART:20380119T091407
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DTSTART:20091231T230000
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BEGIN:VEVENT
DTSTAMP:20250624T152725Z
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DTSTART;TZID=Asia/Dhaka:20250622T140000
DTEND;TZID=Asia/Dhaka:20250622T170000
DESCRIPTION:The IEEE EDS Student Branch Chapter is excited to present a tho
 ught-provoking seminar featuring Dr. Shahriar Shahabuddin as the keynote s
 peaker. Join us for an illuminating session on "Algorithm and Architecture
  Co-optimization for AI-Native 6G Chips." This seminar will delve into the
  cutting-edge intersection of artificial intelligence and next-generation 
 wireless technology\, exploring how algorithm-architecture co-design is un
 locking new levels of performance\, efficiency\, and intelligence in 6G ch
 ip development.\n\nWhether you're passionate about AI hardware\, wireless 
 communication\, or semiconductor innovation\, this session offers a unique
  opportunity to gain insights from the frontier of 6G research. Dr. Shahri
 ar Shahabuddin will guide us through the challenges and breakthroughs shap
 ing the future of AI-driven connectivity.\n\n[]\n\nSpeaker(s): Dr. Shahria
 r Shahabuddin\, \n\nRoom: Room No. 100 (VLSI Design Lab)\, Bldg:  Departme
 nt of Electrical and Electronic Engineering\, University of Dhaka\, Room N
 o. 100 (VLSI Design Lab) Department of Electrical and Electronic Engineeri
 ng\, University of Dhaka\, Dhaka - 1000\, Dhaka\, Dhaka\, Bangladesh\, 100
 0
LOCATION:Room: Room No. 100 (VLSI Design Lab)\, Bldg:  Department of Electr
 ical and Electronic Engineering\, University of Dhaka\, Room No. 100 (VLSI
  Design Lab) Department of Electrical and Electronic Engineering\, Univers
 ity of Dhaka\, Dhaka - 1000\, Dhaka\, Dhaka\, Bangladesh\, 1000
ORGANIZER:ieeeedssbcdu@gmail.com
SEQUENCE:33
SUMMARY:FET100 Celebration Activity - Algorithm and Architecture Co-optimiz
 ation for AI-Native 6G Chips
URL;VALUE=URI:https://events.vtools.ieee.org/m/488557
X-ALT-DESC:Description: <br /><p dir="ltr">The IEEE EDS Student Branch Chap
 ter is excited to present a thought-provoking seminar featuring Dr. Shahri
 ar Shahabuddin as the keynote speaker. Join us for an illuminating session
  on "Algorithm and Architecture Co-optimization for AI-Native 6G Chips." T
 his seminar will delve into the cutting-edge intersection of artificial in
 telligence and next-generation wireless technology\, exploring how algorit
 hm-architecture co-design is unlocking new levels of performance\, efficie
 ncy\, and intelligence in 6G chip development.</p>\n<p><strong>&nbsp\;</st
 rong></p>\n<p dir="ltr">Whether you're passionate about AI hardware\, wire
 less communication\, or semiconductor innovation\, this session offers a u
 nique opportunity to gain insights from the frontier of 6G research. Dr. S
 hahriar Shahabuddin will guide us through the challenges and breakthroughs
  shaping the future of AI-driven connectivity.</p>\n<p><img src="https://e
 vents.vtools.ieee.org/vtools_ui/media/display/97169277-5523-4b33-8ec2-ff78
 a1ec3059" alt="" width="1050" height="591"></p>
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