BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Warsaw BEGIN:DAYLIGHT DTSTART:20180325T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20171029T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20171213T151631Z UID:76151BEE-E018-11E7-833E-0050568D7F66 DTSTART;TZID=Europe/Warsaw:20171218T123000 DTEND;TZID=Europe/Warsaw:20171218T140000 DESCRIPTION:Internet-of-Things (IoT) imposes severe requirements on ultra-l ow power consumption of radio frequency transceivers. Battery life is crit ical in these applications and can be extended by lowering supply voltage to reduce power consumption. In the receiver part of the radio\, the analo g front-end section is the most power-hungry subsystem and has received a lot of attention lately\, mainly from the analog continuous-time point of view. Advances in discrete-time receiver designs\, however\, offer new alt ernatives with simpler and technology-scalable switched-capacitor circuits and easy calibration of intermediate frequency and band-pass selection ba sed on capacitor ratios\, which are less sensitive to process variations. New passive charge-domain switched-capacitor filter topologies and accurat e control of sampling rates\, both of which benefit from technology scalin g and enable easier-to-design low-power solutions\, have been introduced. Another important aspect of the proposed low-power solution is full integr ation of all the RF building blocks to reduce system costs. These new band -pass filters are highly selective and enable saw-less solutions for eithe r low-power or high-performance applications. The super-heterodyne receive r is the architecture of choice with less issues regarding flicker noise\, second-order linearity and time-varying DC offsets\, besides not requirin g the bulky external filters used in the past. This tutorial presents the recently developed concepts in discrete-time receivers leading to an ultra -low-power state-of-the-art Bluetooth Low Energy receiver which was implem ented in low cost TSMC 28 nm bulk CMOS.\n\nSpeaker(s): Robert Bogdan Stasz ewski\, Prof.\, \, Robert Bogdan Staszewski\, Prof.\, \n\nAgenda: \n12:30 - 14:00\,\n\nH-113\, B4\, AGH University of Science and Technology\, Craco w\, Poland\n\nRoom: H-113\, Bldg: B4\, AGH University of Science and Techn ology\, Cracow\, Malopolskie\, Poland\, 30-059 LOCATION:Room: H-113\, Bldg: B4\, AGH University of Science and Technology\ , Cracow\, Malopolskie\, Poland\, 30-059 ORGANIZER:kasinski@agh.edu.pl SEQUENCE:1 SUMMARY:Design of Discrete-Time Receivers for the Internet-of-Things URL;VALUE=URI:https://events.vtools.ieee.org/m/49106 X-ALT-DESC:Description: <br /><h2><span style="font-size: 10pt\;">Internet- of-Things (IoT) imposes severe requirements on ultra-low power consumption of radio frequency transceivers. Battery life is critical in these applic ations and can be extended by lowering supply voltage to reduce power cons umption. In the receiver part of the radio\, the analog front-end section is the most power-hungry subsystem and has received a lot of attention lat ely\, mainly from the analog continuous-time point of view. Advances in di screte-time receiver designs\, however\, offer new alternatives with simpl er and technology-scalable switched-capacitor circuits and easy calibratio n of intermediate frequency and band-pass selection based on capacitor rat ios\, which are less sensitive to process variations. New passive charge-d omain switched-capacitor filter topologies and accurate control of samplin g rates\, both of which benefit from technology scaling and enable easier- to-design low-power solutions\, have been introduced. Another important as pect of the proposed low-power solution is full integration of all the RF building blocks to reduce system costs. These new band-pass filters are hi ghly selective and enable saw-less solutions for either low-power or high- performance applications. The super-heterodyne receiver is the architectur e of choice with less issues regarding flicker noise\, second-order linear ity and time-varying DC offsets\, besides not requiring the bulky external filters used in the past. This tutorial presents the recently developed c oncepts in discrete-time receivers leading to an ultra-low-power state-of- the-art Bluetooth Low Energy receiver which was implemented in low cost TS MC 28 nm <em>bulk</em> CMOS.</span></h2><br /><br />Agenda: <br /><p>12:30 - 14:00\,</p>\n<p>H-113\, B4\, AGH University of Science and Technology\, Cracow\, Poland</p> END:VEVENT END:VCALENDAR