BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Berlin BEGIN:DAYLIGHT DTSTART:20250330T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20251026T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250915T125834Z UID:CF184B9E-1BD9-40A5-9875-E32F641EA983 DTSTART;TZID=Europe/Berlin:20250911T160000 DTEND;TZID=Europe/Berlin:20250911T183000 DESCRIPTION:Despite the much debated end of Moore's Law\, CMOS scaling stil l maintains economic relevance with 3nm finFET SoCs already in the marketp lace for over a year and 2nm gate-all-around SoCs anticipated this year. M odest feature size reduction and design/technology innovations co-optimize d for primarily logic scaling continue to offer compelling node-to-node po wer\, performance\, area\, and cost benefits. In this tutorial\, we will s tart with a walk through memory lane\, recounting a brief history of trans istor evolution to motivate the migration from the planar MOSFET to the fu lly depleted FinFET. We will summarize the key process technology elements that have enabled the finFET CMOS nodes\, highlighting the resulting devi ce technology characteristics and challenges. This will set the context fo r motivating the introduction of the gate-all-around transistor architectu re\, namely nanoribbons or nanosheets\, and unveiling the magic of how the se devices are fabricated. We will then shift to summarize the challenges that CMOS technology scaling has imposed on analog design. To address the growing effort required for analog/mixed-signal design closure\, we will c over design strategies on how analog design has adapted and thrived throug hout decades of increasingly unfriendly CMOS scaling\, including the migra tion to heterogeneous integration as prophesied by Gordon Moore's seminal 1965 paper.\n\nCo-sponsored by: NXP Semiconductors\n\nSpeaker(s): Alvin Lo ke\n\nBldg: NXP Semiconductors Germany GmbH\, Schatzbogen 7\, Munich\, Bay ern\, Germany\, 81829\, Virtual: https://events.vtools.ieee.org/m/493693 LOCATION:Bldg: NXP Semiconductors Germany GmbH\, Schatzbogen 7\, Munich\, B ayern\, Germany\, 81829\, Virtual: https://events.vtools.ieee.org/m/493693 ORGANIZER:moustafa.nawito@gmail.com SEQUENCE:17 SUMMARY:Distinguished Lecture: Alvin Loke – "The Road to Gate-All-Around and Its Impact on Analog Design" URL;VALUE=URI:https://events.vtools.ieee.org/m/493693 X-ALT-DESC:Description: <br /><p>Despite the much debated end of Moore's La w\, CMOS scaling still maintains economic relevance with 3nm finFET SoCs a lready in the marketplace for over a year and 2nm gate-all-around SoCs ant icipated this year. Modest feature size reduction and design/technology in novations co-optimized for primarily logic scaling continue to offer compe lling node-to-node power\, performance\, area\, and cost benefits. In this tutorial\, we will start with a walk through memory lane\, recounting a b rief history of transistor evolution to motivate the migration from the pl anar MOSFET to the fully depleted FinFET. We will summarize the key proces s technology elements that have enabled the finFET CMOS nodes\, highlighti ng the resulting device technology characteristics and challenges. This wi ll set the context for motivating the introduction of the gate-all-around transistor architecture\, namely nanoribbons or nanosheets\, and unveiling the magic of how these devices are fabricated. We will then shift to summ arize the challenges that CMOS technology scaling has imposed on analog de sign. To address the growing effort required for analog/mixed-signal desig n closure\, we will cover design strategies on how analog design has adapt ed and thrived throughout decades of increasingly unfriendly CMOS scaling\ , including the migration to heterogeneous integration as prophesied by Go rdon Moore's seminal 1965 paper.</p> END:VEVENT END:VCALENDAR