BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Kolkata BEGIN:STANDARD DTSTART:19451014T230000 TZOFFSETFROM:+0630 TZOFFSETTO:+0530 TZNAME:IST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250723T082155Z UID:0DA9D93A-5EEF-4919-A621-8D794AF5EE43 DTSTART;TZID=Asia/Kolkata:20250310T140000 DTEND;TZID=Asia/Kolkata:20250310T160000 DESCRIPTION:The Department of Electrical\, Electronics\, and Communication Engineering (EECE) at GITAM School of Technology\, Hyderabad\, in associat ion with the IEEE GITAM student branch chapter\, hosted a distinguished gu est lecture on ‘Advanced Semiconductor Packaging Techniques’ by Dr. Ve nkata Mokkapati\, Global Director & Application Engineering at AT&S AG\, A ustria.\n\nDr. Mokkapati provided in-depth insights into cutting-edge semi conductor packaging technologies\, including 2D\, 2D+\, 2.5D\, 3D\, 3.5D\, and the latest 4D packaging\, which integrates components through substra te folding or bending for enhanced electrical interconnectivity. He highli ghted the demand for advanced build-up materials used in contemporary pack age structures such as BGA\, CSP\, and coreless packaging\, emphasizing th e critical factors of fine line and space\, fine via pitch\, low warpage d uring cure and reflow\, and high insulation reliability.\n\nDiscussing the future of advanced packaging and IC substrates\, Dr. Mokkapati elaborated on innovations such as D2 connection\, larger body sizes\, coefficient of thermal expansion (CTE) mismatch solutions\, power delivery advancements\ , and improved thermal dissipation. He also addressed key developments in semiconductor technology\, covering major technology blocks\, top industry players\, and the evolving AI value chain.\n\nThe lecture further delved into significant industry transformations\, ABF substrate construction\, h igh-performance computing (HPC) architecture\, and the semiconductor chips driving future innovations. Dr. Mokkapati also shared insights on India ’s emerging semiconductor manufacturing landscape\, citing projects by l eading companies such as Micron\, Renesas\, Stars\, Kaynes Technology\, TA TA-PSMC\, and Adani-Tower Semiconductor.\n\nEngaging with the students\, D r. Mokkapati responded to queries from EECE students\, fostering a dynamic exchange of knowledge and ideas. The event concluded with a felicitation ceremony led by Prof. T. Madhavi\, Head of the EECE Department\, and Prof. Prasantha R. Mudimela\, the Convenor\, who honored Dr. Mokkapati for his invaluable contributions.\n\nSpeaker(s): Mokkapati\, \n\nRoom: 303\, Bldg: J\, Rudraram\, Patacheru mandal\, Sangareddy\, Hyderabad\, Hyderabad\, An dhra Pradesh\, India\, 502329 LOCATION:Room: 303\, Bldg: J\, Rudraram\, Patacheru mandal\, Sangareddy\, H yderabad\, Hyderabad\, Andhra Pradesh\, India\, 502329 ORGANIZER:pmuidimel@gitam.edu SEQUENCE:20 SUMMARY:Advanced Semiconductor Packaging Techniques URL;VALUE=URI:https://events.vtools.ieee.org/m/493938 X-ALT-DESC:Description: <br /><p class="MsoNormal" style="text-align: justi fy\;"><span style="font-size: 12.0pt\; line-height: 107%\; font-family: 'T imes New Roman'\,serif\;">The Department of Electrical\, Electronics\, and Communication Engineering (EECE) at GITAM School of Technology\, Hyderaba d\, in association with the IEEE GITAM student branch chapter\, hosted a d istinguished guest lecture on &lsquo\;Advanced Semiconductor Packaging Tec hniques&rsquo\; by Dr. Venkata Mokkapati\, Global Director &amp\; Applicat ion Engineering at AT&amp\;S AG\, Austria.</span></p>\n<p class="MsoNormal " style="text-align: justify\;"><span style="font-size: 12.0pt\; line-heig ht: 107%\; font-family: 'Times New Roman'\,serif\;">Dr. Mokkapati provided in-depth insights into cutting-edge semiconductor packaging technologies\ , including 2D\, 2D+\, 2.5D\, 3D\, 3.5D\, and the latest 4D packaging\, wh ich integrates components through substrate folding or bending for enhance d electrical interconnectivity. He highlighted the demand for advanced bui ld-up materials used in contemporary package structures such as BGA\, CSP\ , and coreless packaging\, emphasizing the critical factors of fine line a nd space\, fine via pitch\, low warpage during cure and reflow\, and high insulation reliability.</span></p>\n<p class="MsoNormal" style="text-align : justify\;"><span style="font-size: 12.0pt\; line-height: 107%\; font-fam ily: 'Times New Roman'\,serif\;">Discussing the future of advanced packagi ng and IC substrates\, Dr. Mokkapati elaborated on innovations such as D2 connection\, larger body sizes\, coefficient of thermal expansion (CTE) mi smatch solutions\, power delivery advancements\, and improved thermal diss ipation. He also addressed key developments in semiconductor technology\, covering major technology blocks\, top industry players\, and the evolving AI value chain.</span></p>\n<p class="MsoNormal" style="text-align: justi fy\;"><span style="font-size: 12.0pt\; line-height: 107%\; font-family: 'T imes New Roman'\,serif\;">The lecture further delved into significant indu stry transformations\, ABF substrate construction\, high-performance compu ting (HPC) architecture\, and the semiconductor chips driving future innov ations. Dr. Mokkapati also shared insights on India&rsquo\;s emerging semi conductor manufacturing landscape\, citing projects by leading companies s uch as Micron\, Renesas\, Stars\, Kaynes Technology\, TATA-PSMC\, and Adan i-Tower Semiconductor.</span></p>\n<p class="MsoNormal" style="text-align: justify\;"><span style="font-size: 12.0pt\; line-height: 107%\; font-fami ly: 'Times New Roman'\,serif\;">Engaging with the students\, Dr. Mokkapati responded to queries from EECE students\, fostering a dynamic exchange of knowledge and ideas. The event concluded with a felicitation ceremony led by Prof. T. Madhavi\, Head of the EECE Department\, and Prof. Prasantha R . Mudimela\, the Convenor\, who honored Dr. Mokkapati for his invaluable&n bsp\;contributions.</span></p> END:VEVENT END:VCALENDAR