BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
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BEGIN:VEVENT
DTSTAMP:20260411T064748Z
UID:A1F58B5D-D789-4384-9D4F-717FFC56A893
DTSTART;TZID=Asia/Kolkata:20260302T090000
DTEND;TZID=Asia/Kolkata:20260303T190000
DESCRIPTION:IEEE EPT Conference 206 is an international conference organize
 d by the IEEE EPS Delhi Chapter and co-sponsored by the IEEE Electronics P
 ackaging Society (EPS) along with Manav Rachna International Institute of 
 Research &amp; Studies.\n\nSet in the backdrop of a verdant\, green campus in 
 the Aravalli hills\, the event is hosted at Manav Rachana International In
 stitute of Research &amp; Studies\, Faridabad\, Delhi-NCR. It will feature key
 notes\, tutorials\, technical sessions\, invited talks\, panels\, workshop
 s\, exhibitions\, and networking activities.\n\nTopics include modules\, c
 omponents\, materials\, equipment technology\, assembly\, reliability\, in
 terconnect design\, device and systems packaging\, heterogeneous integrati
 on\, wafer-level packaging\, flexible electronics\, LED\, IoT\, 5G\, emerg
 ing technologies\, 2.5D/3D integration technology\, smart manufacturing\, 
 automation\, and AI. Planned in tandem with the Gujarat Semiconnect (SMarc
 h 5-6\, 2026 )\, the event is expected to pull in ~250 academia/industry p
 articipants.\n\nCo-sponsored by: Manav Rachna International Institute of R
 esearch &amp; Studies\, Faridabad\n\nSpeaker(s): Dr Ashwini\, Dr Umesh\, \n\nA
 genda: \nRef conference URL\n\nhttp://www.eptc.in\n\nManav Rachna Internat
 ional Institute of Research &amp; Studies\, Suraj Kund Badkhal Road\, Sector 4
 3\, Faridabad\, Haryana\, India\, 121004
LOCATION:Manav Rachna International Institute of Research &amp; Studies\, Suraj
  Kund Badkhal Road\, Sector 43\, Faridabad\, Haryana\, India\, 121004
ORGANIZER:aka.xli@outlook.com
SEQUENCE:25
SUMMARY:1st International Conference on Electronics &amp; Packaging Technologie
 s (EPDMC 2026) | EPDMC.in | 2nd-3rd March
URL;VALUE=URI:https://events.vtools.ieee.org/m/494495
X-ALT-DESC:Description: &lt;br /&gt;&lt;div&gt;\n&lt;div&gt;\n&lt;div&gt;\n&lt;p&gt;IEEE EPT Conference 2
 06 is an international conference organized by the IEEE EPS Delhi Chapter 
 and co-sponsored by the IEEE Electronics Packaging Society (EPS) along wit
 h Manav Rachna International Institute of Research &amp;amp\; Studies.&lt;/p&gt;\n&lt;/
 div&gt;\n&lt;div&gt;\n&lt;p&gt;Set in the backdrop of a verdant\, green campus in the Ara
 valli hills\, the event is hosted at Manav Rachana International Institute
  of Research &amp;amp\; Studies\, Faridabad\, Delhi-NCR. It will feature keyno
 tes\, tutorials\, technical sessions\, invited talks\, panels\, workshops\
 , exhibitions\, and networking activities.&lt;/p&gt;\n&lt;/div&gt;\n&lt;div&gt;\n&lt;p&gt;Topics i
 nclude modules\, components\, materials\, equipment technology\, assembly\
 , reliability\, interconnect design\, device and systems packaging\, heter
 ogeneous integration\, wafer-level packaging\, flexible electronics\, LED\
 , IoT\, 5G\, emerging technologies\, 2.5D/3D integration technology\, smar
 t manufacturing\, automation\, and AI. Planned in tandem with the Gujarat 
 Semiconnect (SMarch 5-6\, 2026 )\, the event is expected to pull in ~250 a
 cademia/industry participants.&lt;/p&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;&lt;br /&gt;&lt;br /&gt;Agen
 da: &lt;br /&gt;&lt;p&gt;Ref conference URL&lt;/p&gt;\n&lt;p&gt;&lt;a href=&quot;http://www.eptc.in&quot;&gt;http:
 //www.eptc.in&lt;/a&gt;&lt;/p&gt;\n&lt;p&gt;&amp;nbsp\;&lt;/p&gt;
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