BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Colombo BEGIN:DAYLIGHT DTSTART:20380119T084407 TZOFFSETFROM:+0530 TZOFFSETTO:+0530 RRULE:FREQ=YEARLY;BYDAY=3TU;BYMONTH=1 TZNAME:+0530 END:DAYLIGHT BEGIN:STANDARD DTSTART:20060415T000000 TZOFFSETFROM:+0600 TZOFFSETTO:+0530 RRULE:FREQ=YEARLY;BYDAY=3SA;BYMONTH=4 TZNAME:+0530 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250731T063003Z UID:503BDA59-DC1D-4C5C-8C17-19CC61D8EACA DTSTART;TZID=Asia/Colombo:20250607T090000 DTEND;TZID=Asia/Colombo:20250607T160000 DESCRIPTION:[]\n\nThe VLSI Workshop II\, conducted by Synopsys\, is designe d to provide participants with hands-on experience in industry-standard El ectronic Design Automation (EDA) tools used in power and timing analysis w orkflows. The workshop covers PrimePower for detailed gate-level power ana lysis\, PrimePower RTL for early-stage power estimation\, and PrimeTime fo r comprehensive static timing analysis. These sessions will help participa nts develop a strong understanding of essential methodologies applied in r eal-world VLSI design environments.\n\nThis workshop is ideal for undergra duates passionate about VLSI and digital system design\, offering them exp osure to advanced tools widely used in the semiconductor industry. By enga ging in practical exercises and guided analysis\, participants will gain v aluable insights into optimizing designs for power efficiency and timing a ccuracy. With a focus on bridging academic concepts with professional appl ications\, the workshop provides an excellent opportunity to enhance both technical knowledge and practical skills in modern chip design workflows.\ n\nCo-sponsored by: Synopsys Lanka (Pvt) Ltd\n\nBldg: Computer Lab 02\, Fa culty of Engineering\, University of Peradeniya\, Peradeniya\, Sri Lanka\, Sri Lanka\, 20400 LOCATION:Bldg: Computer Lab 02\, Faculty of Engineering\, University of Per adeniya\, Peradeniya\, Sri Lanka\, Sri Lanka\, 20400 ORGANIZER:ieeepdn@gmail.com SEQUENCE:0 SUMMARY:VLSI Workshop 2 by Synopsys URL;VALUE=URI:https://events.vtools.ieee.org/m/495035 X-ALT-DESC:Description: <br /><p data-start="102" data-end="656"><img style ="display: block\; margin-left: auto\; margin-right: auto\;" src="https:// events.vtools.ieee.org/vtools_ui/media/display/d11f79c6-aba9-4db3-9c7f-91e 5c6f53df8" alt="" width="270" height="382"></p>\n<p data-start="102" data- end="656">The <strong data-start="106" data-end="126">VLSI Workshop II</st rong>\, conducted by <strong data-start="141" data-end="153">Synopsys</str ong>\, is designed to provide participants with hands-on experience in ind ustry-standard Electronic Design Automation (EDA) tools used in power and timing analysis workflows. The workshop covers <strong data-start="343" da ta-end="357">PrimePower</strong> for detailed gate-level power analysis\, <strong data-start="398" data-end="416">PrimePower RTL</strong> for early- stage power estimation\, and <strong data-start="455" data-end="468">Prime Time</strong> for comprehensive static timing analysis. These sessions wil l help participants develop a strong understanding of essential methodolog ies applied in real-world VLSI design environments.</p>\n<p data-start="65 8" data-end="1213">This workshop is ideal for undergraduates passionate ab out <strong data-start="717" data-end="751">VLSI and digital system design </strong>\, offering them exposure to advanced tools widely used in the se miconductor industry. By engaging in practical exercises and guided analys is\, participants will gain valuable insights into optimizing designs for power efficiency and timing accuracy. With a focus on bridging academic co ncepts with professional applications\, the workshop provides an excellent opportunity to enhance both technical knowledge and practical skills in m odern chip design workflows.</p> END:VEVENT END:VCALENDAR