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PRODID:IEEE vTools.Events//EN
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DTSTART:20380119T001407
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DTSTART:20190216T230000
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DTSTAMP:20250806T164703Z
UID:366372BC-179A-4BC0-8328-191E8AEB2EE8
DTSTART;TZID=America/Sao_Paulo:20250814T133000
DTEND;TZID=America/Sao_Paulo:20250814T150000
DESCRIPTION:There will be a presentation providing an overview of the main 
 design verification methods for digital ASICs\, within the context of a co
 mplete development roadmap. The focus will be on the emulation technique\,
  highlighting its particularities and how it differs from other approaches
  such as simulation\, prototyping\, and formal verification.\n\nShort Bio:
  Guilherme Resende Vieira holds a Bachelor's degree in Computer Science fr
 om the Federal University of Minas Gerais (UFMG)\, with 7 years of experie
 nce as a Design Verification Engineer at Cadence Design Systems. He is cur
 rently working as a Lead Design Engineer\, focusing on digital ASIC projec
 ts for Emulation.\n\nSpeaker(s): Guilherme\, \n\nAgenda: \nAugust 14\, 202
 5\, at 1:30 PM\nSeminar Room 1012 – School of Engineering – Federal Un
 iversity of Minas Gerais\n\nRoom: O ChatGPT disse: Seminar Room 1020\, Bld
 g: School of Engineering\, Av. Pres. Antônio Carlos\, 6627\, 80\, Belo Ho
 rizonte\, Minas Gerais\, Brazil\, 31330-670
LOCATION:Room: O ChatGPT disse: Seminar Room 1020\, Bldg: School of Enginee
 ring\, Av. Pres. Antônio Carlos\, 6627\, 80\, Belo Horizonte\, Minas Gera
 is\, Brazil\, 31330-670
ORGANIZER:dalton.colombo@gmail.com
SEQUENCE:9
SUMMARY:Emulation and Verification of Digital Designs
URL;VALUE=URI:https://events.vtools.ieee.org/m/495891
X-ALT-DESC:Description: <br /><p class="cvGsUA direction-ltr align-justify 
 para-style-body"><span class="OYPEnA font-feature-liga-off font-feature-cl
 ig-off font-feature-calt-off text-decoration-none text-strikethrough-none"
 >There will be a presentation providing an overview of the main design ver
 ification methods for digital ASICs\, within the context of a complete dev
 elopment roadmap. The focus will be on the emulation technique\, highlight
 ing its particularities and how it differs from other approaches such as s
 imulation\, prototyping\, and formal verification.</span></p>\n<p class="c
 vGsUA direction-ltr align-justify para-style-body"><span class="OYPEnA fon
 t-feature-liga-off font-feature-clig-off font-feature-calt-off text-decora
 tion-none text-strikethrough-none"><strong data-start="64" data-end="78">S
 hort Bio:</strong> Guilherme Resende Vieira holds a Bachelor's degree in C
 omputer Science from the Federal University of Minas Gerais (UFMG)\, with 
 7 years of experience as a Design Verification Engineer at Cadence Design 
 Systems. He is currently working as a Lead Design Engineer\, focusing on d
 igital ASIC projects for Emulation.</span></p><br /><br />Agenda: <br /><p
 ><strong data-start="42" data-end="73">August 14\, 2025\, at 1:30 PM</stro
 ng><br data-start="73" data-end="76"><strong data-start="76" data-end="158
 " data-is-last-node="">Seminar Room 1012 &ndash\; School of Engineering &n
 dash\; Federal University of Minas Gerais</strong></p>\n<p>&nbsp\;</p>
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