BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT DTSTART:20250309T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20251102T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250825T151255Z UID:46A1F7FB-888C-4A3E-80E8-CF2676DB7027 DTSTART;TZID=America/New_York:20250822T110000 DTEND;TZID=America/New_York:20250822T120000 DESCRIPTION:The Trident Chapter and Nanotech Chapter are pleased to host ED S Distinguished Lecturer Prof. Ramachandra Achar from Carleton University\ , Ottawa\, Canada. Prof. Achar will give a seminar\, "Emerging High-Speed Nanoscale Interconnect Issues and Modelling Challenges" at 11:00 am ET on Friday\, August 22.\n\nThe seminar will be in a hybrid format\, with the i n-person talk in room EECS 1200 on the University of Michigan North Campus in Ann Arbor\, MI\, and a simulcast via Zoom.\n\nProf. Achar will be avai lable before and after the talk for questions and 1-on-1 meetings. To arra nge a meeting\, please contact the hosts.\n\nSEM Trident Chapter (AP03/ED1 5/MTT17/PHO36) [website](https://r4.ieee.org/sem/chapter-iv-trident/)\n\nS peaker(s): Prof. Ram Achar\n\nAgenda: \nWelcome: 11:00 am\n\nPresentation\ n\nQ&A\n\nClosing\n\nIEEE EDS Distinguished Lecture\n\nEmerging High-Speed Nanoscale Interconnect Issues and Modelling Challenges\n\nProf. Ramachand ra Achar\, Ph. D.\, P. Eng.\,\n\nIEEE Fellow\, Fellow EIC\n\nProfessor\, D epartment of Electronics\,\n\nCarleton University\, Ottawa\, Ontario - K1S 5B6\n\nEmail: achar@doe.carleton.ca\nURL: www.doe.carleton.ca/~achar\nAbs tract: With the increasing demands for higher signal speeds coupled with t he need for decreasing feature sizes\, interconnect related signal integri ty effects such as delay\, distortion\, reflections\, crosstalk\, ground b ounce and electromagnetic interference have become the dominant factors li miting the performance of high-speed systems. These effects can be diverse and can seriously impact the design performance at all hierarchical level s including integrated circuits\, printed circuit boards\, multi-chip modu les and backplanes. This talk provides a comprehensive approach for unders tanding the multidisciplinary problem of signal integrity: issues/modeling /analysis in high-speed designs.\n\nBio: Prof. Achar currently is a profes sor in the department of electronics engineering at Carleton University\, Canada (since 2000). He also served in various capacities in leading resea rch labs\, including T. J. Watson Research Center\, IBM\, New York (1995)\ , Larsen and Toubro Engineers Ltd.\, Mysore (1992)\, Central Electronics E ngineering Research Institute\, Pilani\, India (1992) and Indian Institute of Science\, Bangalore\, India (1990). He has published over 250 peer-re viewed articles in international transactions/conferences\, six multimedia books on signal integrity and five chapters in different books and has re ceived numerous prestigious awards recognizing his research contributions. His research interests include signal/power integrity analysis\, high-spe ed interconnects\, circuit simulation\, parallel and numerical algorithms and microwave/RF/EMC/EMI mixed-domain analysis. Prof. Achar currently serv es as a Distinguished Lecturer of the IEEE Electronic Devices Society and IEEE Electronic Packaging Society\, Chair of the Distinguished Lecturer of program of IEEE EMC Society. He also serves in several executive/steering /advisory/technical-program committees of several leading IEEE internation al conferences\, such as EPEPS\, EDAPS and SPI etc. Dr. Achar is a practi cing professional engineer of Ontario\, a Fellow of Engineers Institute of Canada and IEEE.\n\nRoom: 1200 EECS\, Bldg: EECS Building\, 1301 Beal Ave \, University of Michigan North Campus\, Ann Arbor\, Michigan\, United Sta tes\, 48109\, Virtual: https://events.vtools.ieee.org/m/496118 LOCATION:Room: 1200 EECS\, Bldg: EECS Building\, 1301 Beal Ave\, University of Michigan North Campus\, Ann Arbor\, Michigan\, United States\, 48109\, Virtual: https://events.vtools.ieee.org/m/496118 ORGANIZER:yms@umich.edu SEQUENCE:37 SUMMARY:IEEE EDS Distinguished Lecture - Prof. Ramachandra Achar URL;VALUE=URI:https://events.vtools.ieee.org/m/496118 X-ALT-DESC:Description: <br /><p>The Trident Chapter and Nanotech Chapter a re pleased to host EDS Distinguished Lecturer Prof. Ramachandra Achar from Carleton University\, Ottawa\, Canada. Prof. Achar will give a seminar\, &nbsp\;"<strong>Emerging High-Speed Nanoscale Interconnect Issues and Mode lling Challenges</strong>"&nbsp\;at 11:00 am ET on Friday\, August 22.</p> \n<p>The seminar will be in a hybrid format\, with the in-person talk in r oom EECS 1200 on the University of Michigan North Campus in Ann Arbor\, MI \, and a simulcast via Zoom.</p>\n<p>Prof. Achar will be available before and after the talk for questions and 1-on-1 meetings. To arrange a meeting \, please contact the hosts.</p>\n<p>SEM Trident Chapter (AP03/ED15/MTT17/ PHO36) <a href="https://r4.ieee.org/sem/chapter-iv-trident/">website</a></ p><br /><br />Agenda: <br /><p>Welcome: 11:00 am</p>\n<p>Presentation</p>\ n<p>Q&amp\;A</p>\n<p>Closing</p>\n<p class="MsoNormal" style="text-align: center\;" align="center"><strong><em style="mso-bidi-font-style: normal\;" ><span lang="EN-CA" style="font-size: 16.0pt\; line-height: 115%\; color: black\; mso-themecolor: text1\; mso-ansi-language: EN-CA\;">IEEE EDS Disti nguished Lecture</span></em></strong></p>\n<p><strong><span style="font-si ze: 14.0pt\; line-height: 115%\; font-family: 'Calibri'\,sans-serif\; mso- ascii-theme-font: minor-latin\; mso-fareast-font-family: Calibri\; mso-far east-theme-font: minor-latin\; mso-hansi-theme-font: minor-latin\; mso-bid i-font-family: 'Times New Roman'\; mso-bidi-theme-font: minor-bidi\; color : black\; mso-themecolor: text1\; mso-ansi-language: EN-US\; mso-fareast-l anguage: EN-US\; mso-bidi-language: AR-SA\;">Emerging High-Speed Nanoscale Interconnect Issues and Modelling Challenges</span></strong></p>\n<table style="border-collapse: collapse\; width: 100%\; border-width: 1px\; borde r-style: none\;" border="1"><colgroup><col style="width: 24.9513%\;"><col style="width: 75.0487%\;"></colgroup>\n<tbody>\n<tr>\n<td style="text-alig n: left\;">\n<p style="margin: 0in\; text-align: left\;" align="center"><i mg src="https://events.vtools.ieee.org/vtools_ui/media/display/cad852c8-6c 94-4a51-81be-34e620188d10"></p>\n</td>\n<td>\n<p style="margin: 0in\; text -align: left\;" align="center"><strong><span lang="EN-CA" style="font-size : 12.0pt\; font-family: 'Times New Roman'\,serif\; color: windowtext\;">Pr of. Ramachandra Achar\, </span></strong><span lang="EN-CA" style="font-siz e: 12.0pt\; font-family: 'Times New Roman'\,serif\;">Ph. D.\, P. Eng.\, </ span></p>\n<p style="margin: 0in\; text-align: left\;" align="center"><spa n lang="EN-CA" style="font-size: 12.0pt\; font-family: 'Times New Roman'\, serif\;">IEEE Fellow\, Fellow EIC</span></p>\n<p class="MsoNormal" style=" margin-bottom: 0in\; text-align: left\;" align="center"><span style="font- size: 12.0pt\; line-height: 115%\; font-family: 'Times New Roman'\,serif\; mso-bidi-theme-font: minor-bidi\;">Professor\, Department of Electronics\ ,</span></p>\n<p class="MsoNormal" style="margin-bottom: 0in\; text-align: left\;" align="center"><span style="font-size: 12.0pt\; line-height: 115% \; font-family: 'Times New Roman'\,serif\; mso-bidi-theme-font: minor-bidi \;">Carleton University\, Ottawa\, Ontario - K1S 5B6</span></p>\n<p class= "MsoNormal" style="margin-bottom: 0in\; text-align: left\;" align="center" ><span style="font-size: 12.0pt\; line-height: 115%\; font-family: 'Times New Roman'\,serif\; mso-bidi-theme-font: minor-bidi\;">Email: </span><a hr ef="mailto:achar@doe.carleton.ca"><span style="font-size: 12.0pt\; line-he ight: 115%\; font-family: 'Times New Roman'\,serif\; mso-bidi-theme-font: minor-bidi\;">achar@doe.carleton.ca</span></a></p>\n<span style="font-size : 12.0pt\; line-height: 115%\; font-family: 'Times New Roman'\,serif\; mso -fareast-font-family: Calibri\; mso-fareast-theme-font: minor-latin\; mso- bidi-theme-font: minor-bidi\; mso-ansi-language: EN-US\; mso-fareast-langu age: EN-US\; mso-bidi-language: AR-SA\;">URL:<span style="mso-tab-count: 1 \;">&nbsp\;&nbsp\; </span></span><span style="font-size: 11.0pt\; line-hei ght: 115%\; font-family: 'Calibri'\,sans-serif\; mso-ascii-theme-font: min or-latin\; mso-fareast-font-family: Calibri\; mso-fareast-theme-font: mino r-latin\; mso-hansi-theme-font: minor-latin\; mso-bidi-font-family: 'Times New Roman'\; mso-bidi-theme-font: minor-bidi\; mso-ansi-language: EN-US\; mso-fareast-language: EN-US\; mso-bidi-language: AR-SA\;"><a href="http:/ /www.doe.carleton.ca/~achar"><span style="font-size: 12.0pt\; line-height: 115%\; font-family: 'Times New Roman'\,serif\; mso-bidi-theme-font: minor -bidi\;">www.doe.carleton.ca/~achar</span></a></span></td>\n</tr>\n</tbody >\n</table>\n<p class="MsoNormal" style="text-align: justify\;"><strong st yle="mso-bidi-font-weight: normal\;"><span style="font-size: 12.0pt\; line -height: 115%\;">Abstract:</span></strong><span style="font-size: 12.0pt\; line-height: 115%\;"> With the increasing demands for higher signal speed s coupled with the need for decreasing feature sizes\, interconnect relate d signal integrity effects such as delay\, distortion\, reflections\, cros stalk\, ground bounce and electromagnetic interference have become the dom inant factors limiting the performance of high-speed systems. These effect s can be diverse and can seriously impact the design performance at all hi erarchical levels including integrated circuits\, printed circuit boards\, multi-chip modules and backplanes. This talk provides a comprehensive app roach for understanding the multidisciplinary problem of signal integrity: issues/modeling/analysis in high-speed designs.</span></p>\n<p class="Mso Normal" style="text-align: justify\;"><strong style="mso-bidi-font-weight: normal\;"><span style="font-size: 12.0pt\; line-height: 115%\;">Bio:</spa n></strong><span style="font-size: 12.0pt\; line-height: 115%\;"> </span>< span style="font-size: 12.0pt\; line-height: 115%\; mso-fareast-font-famil y: 'Times New Roman'\;">Prof. Achar currently is a professor in the depart ment of electronics engineering at Carleton University\, Canada (since 200 0). He also served in various capacities in leading research labs\, includ ing T. J. Watson Research Center\, IBM\, New York (1995)\, Larsen and Toub ro Engineers Ltd.\, Mysore (1992)\, Central Electronics Engineering Resear ch Institute\, Pilani\, India (1992) and Indian Institute of Science\, Ban galore\, India (1990). </span><span style="font-size: 12.0pt\; line-height : 115%\;"><span style="mso-spacerun: yes\;">&nbsp\;</span>He has </span><s pan style="font-size: 12.0pt\; line-height: 115%\; mso-fareast-font-family : 'Times New Roman'\;">published over 250 peer-reviewed articles in intern ational transactions/conferences\, six multimedia books on signal integrit y and five chapters in different books and has received numerous prestigio us awards recognizing his research contributions. His research interests i nclude signal/power integrity analysis\, high-speed interconnects\, circui t simulation\, parallel and numerical algorithms and microwave/RF/EMC/EMI mixed-domain analysis.</span><span style="font-size: 12.0pt\; line-height: 115%\;"> </span><span style="font-size: 12.0pt\; line-height: 115%\; mso- fareast-font-family: 'Times New Roman'\;">Prof. Achar currently serves as a Distinguished Lecturer of the IEEE Electronic Devices Society and IEEE E lectronic Packaging Society\, Chair of the Distinguished Lecturer of progr am of IEEE EMC Society. He also serves in several executive/steering/advis ory/technical-program committees of several leading IEEE international con ferences\, such as EPEPS\, EDAPS and SPI etc. <span style="mso-spacerun: y es\;">&nbsp\;</span>Dr. Achar is a practicing professional engineer of Ont ario\, a Fellow of Engineers Institute of Canada and IEEE. </span></p> END:VEVENT END:VCALENDAR