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BEGIN:VEVENT
DTSTAMP:20250903T152108Z
UID:8791933D-FBA6-42ED-97CF-B38E5737463A
DTSTART;TZID=Asia/Kolkata:20250707T094000
DTEND;TZID=Asia/Kolkata:20250808T164000
DESCRIPTION:The two-day workshop titled “VLSI for Beginners – From Basi
 cs to Real World Design”\, organized by the Department of Electronics an
 d Communication Engineering\, TKR College of Engineering and Technology in
  association with the IEEE CAS Student Branch Chapter (SBC60030787) and Ch
 ipIN Centre\, CDAC\, was held on 7th and 8th July 2025. On Day 1 (7th July
  2025)\, the event commenced with an inaugural session at 9:30 AM\, attend
 ed by dignitaries including the Principal\, Dean Academics\, Controller of
  Examinations\, HoD-ECE\, and the IEEE CAS Faculty Coordinator\, who empha
 sized the significance of VLSI in modern electronics. The forenoon technic
 al sessions began with Dr. P. Kalyani delivering a comprehensive talk on C
 MOS basics and VLSI design flow\, followed by Dr. B. Srikanth’s session 
 on CMOS inverters and common-source amplifiers. In the afternoon\, student
 s engaged in a hands-on session using Cadence ADE\, where they designed an
 d simulated CMOS inverters\, analyzing voltage transfer characteristics an
 d DC biasing.\n\nOn Day 2 (8th July 2025)\, Dr. B. Srikanth conducted a se
 ssion on analog layout design\, introducing students to layout design rule
 s\, DRC\, LVS\, and parasitic effects. This was followed by a session by D
 r. P. Kalyani on career opportunities in the VLSI industry\, where student
 s gained insights into job roles\, skillsets\, and roadmap for entering th
 e semiconductor domain. The afternoon hands-on session involved AC analysi
 s of common-source amplifiers using Cadence\, gain-bandwidth calculation\,
  and layout implementation with DRC validation. Concepts such as Miller ef
 fect\, layout-dependent effects\, and pole-zero placement were discussed d
 uring live demos. The workshop concluded with a valedictory session at 4:3
 0 PM\, where participants shared their feedback and received certificates.
  A total of 81 B.Tech ECE students participated\, gaining valuable knowled
 ge and exposure to both theory and practical aspects of VLSI design.\n\nAg
 enda: \n“VLSI for Beginners – From Basics to Real World Design”\nhel
 d on 7th &amp; 8th July 2025 at TKR College of Engineering and Technology\, or
 ganized by the IEEE CAS Student Branch Chapter (SBC60030787) in associatio
 n with CHIPIN Centre\, CDAC and ECE Department:\n-------------------------
 --------------------------------------\n\nDay 1 – 7th July 2025 (Monday)
 \n\nTime	Session Details\n09:30 AM – 10:00 AM	Inaugural Session\nWelcome
  by dignitaries – Principal\, Dean\, HoD\, IEEE Coordinator\n10:00 AM 
 – 11:30 AM	Session I: Introduction to VLSI &amp; CMOS Basics\nSpeaker: Dr. P
 . Kalyani\n11:45 AM – 01:00 PM	Session II: CMOS Inverter &amp; Common Source
  Amplifier\nSpeaker: Dr. B. Srikanth\n01:00 PM – 02:00 PM	Lunch Break\n0
 2:00 PM – 04:30 PM	Hands-on Session I: Cadence ADE – Inverter Simulati
 on &amp; DC Biasing\n---------------------------------------------------------
 ------\n\nDay 2 – 8th July 2025 (Tuesday)\n\nTime	Session Details\n09:30
  AM – 11:00 AM	Session IV: Layout Design\, DRC &amp; LVS Concepts\nSpeaker: 
 Dr. B. Srikanth\n11:15 AM – 01:00 PM	Session V: Career Opportunities in 
 VLSI Industry\nSpeaker: Dr. P. Kalyani\n01:00 PM – 02:00 PM	Lunch Break\
 n02:00 PM – 04:30 PM	Hands-on Session II: AC Analysis &amp; Layout Design in
  Cadence\n04:30 PM onwards	Valedictory Session &amp; Certificate Distribution\
 n\nTKR College of Engineering and Technology Meerpet\, hyderabad\, Andhra 
 Pradesh\, India
LOCATION:TKR College of Engineering and Technology Meerpet\, hyderabad\, An
 dhra Pradesh\, India
ORGANIZER:nagamahal@gmail.com
SEQUENCE:62
SUMMARY:VLSI for Beginners – From Fundamentals to Real-World Tools: A Han
 ds-on Workshop Report”
URL;VALUE=URI:https://events.vtools.ieee.org/m/496740
X-ALT-DESC:Description: &lt;br /&gt;&lt;p data-start=&quot;224&quot; data-end=&quot;1259&quot;&gt;The&amp;nbsp\
 ;&lt;strong data-start=&quot;228&quot; data-end=&quot;248&quot;&gt;two-day workshop&lt;/strong&gt; titled 
 &lt;strong data-start=&quot;256&quot; data-end=&quot;315&quot;&gt;&amp;ldquo\;VLSI for Beginners &amp;ndash\
 ; From Basics to Real World Design&amp;rdquo\;&lt;/strong&gt;\, organized by the Dep
 artment of Electronics and Communication Engineering\, TKR College of Engi
 neering and Technology in association with the IEEE CAS Student Branch Cha
 pter (SBC60030787) and ChipIN Centre\, CDAC\, was held on &lt;strong data-sta
 rt=&quot;540&quot; data-end=&quot;565&quot;&gt;7th and 8th July 2025&lt;/strong&gt;. On &lt;strong data-st
 art=&quot;570&quot; data-end=&quot;595&quot;&gt;Day 1 (7th July 2025)&lt;/strong&gt;\, the event commen
 ced with an inaugural session at 9:30 AM\, attended by dignitaries includi
 ng the Principal\, Dean Academics\, Controller of Examinations\, HoD-ECE\,
  and the IEEE CAS Faculty Coordinator\, who emphasized the significance of
  VLSI in modern electronics. The forenoon technical sessions began with Dr
 . P. Kalyani delivering a comprehensive talk on CMOS basics and VLSI desig
 n flow\, followed by Dr. B. Srikanth&amp;rsquo\;s session on CMOS inverters an
 d common-source amplifiers. In the afternoon\, students engaged in a hands
 -on session using &lt;strong data-start=&quot;1134&quot; data-end=&quot;1149&quot;&gt;Cadence ADE&lt;/s
 trong&gt;\, where they designed and simulated CMOS inverters\, analyzing volt
 age transfer characteristics and DC biasing.&lt;/p&gt;\n&lt;p data-start=&quot;1261&quot; dat
 a-end=&quot;2206&quot;&gt;On &lt;strong data-start=&quot;1264&quot; data-end=&quot;1289&quot;&gt;Day 2 (8th July 
 2025)&lt;/strong&gt;\, Dr. B. Srikanth conducted a session on analog layout desi
 gn\, introducing students to layout design rules\, DRC\, LVS\, and parasit
 ic effects. This was followed by a session by Dr. P. Kalyani on &lt;strong da
 ta-start=&quot;1482&quot; data-end=&quot;1527&quot;&gt;career opportunities in the VLSI industry&lt;
 /strong&gt;\, where students gained insights into job roles\, skillsets\, and
  roadmap for entering the semiconductor domain. The afternoon hands-on ses
 sion involved &lt;strong data-start=&quot;1678&quot; data-end=&quot;1735&quot;&gt;AC analysis of com
 mon-source amplifiers using Cadence&lt;/strong&gt;\, gain-bandwidth calculation\
 , and layout implementation with DRC validation. Concepts such as Miller e
 ffect\, layout-dependent effects\, and pole-zero placement were discussed 
 during live demos. The workshop concluded with a &lt;strong data-start=&quot;1958&quot;
  data-end=&quot;1992&quot;&gt;valedictory session at 4:30 PM&lt;/strong&gt;\, where participa
 nts shared their feedback and received certificates. A total of &lt;strong da
 ta-start=&quot;2073&quot; data-end=&quot;2099&quot;&gt;81 B.Tech ECE students&lt;/strong&gt; participat
 ed\, gaining valuable knowledge and exposure to both theory and practical 
 aspects of VLSI design.&lt;/p&gt;\n&lt;p data-start=&quot;1261&quot; data-end=&quot;2206&quot;&gt;&lt;img src
 =&quot;https://events.vtools.ieee.org/vtools_ui/media/display/d13a6e65-d46c-4b2
 6-9e3c-3da34df26af4&quot;&gt;&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;br /&gt;&lt;p data-start=&quot;0&quot; data-
 end=&quot;335&quot;&gt;&lt;strong data-start=&quot;57&quot; data-end=&quot;116&quot;&gt;&amp;ldquo\;VLSI for Beginner
 s &amp;ndash\; From Basics to Real World Design&amp;rdquo\;&lt;/strong&gt;&lt;br data-start
 =&quot;116&quot; data-end=&quot;119&quot;&gt;held on &lt;strong data-start=&quot;127&quot; data-end=&quot;150&quot;&gt;7th 
 &amp;amp\; 8th July 2025&lt;/strong&gt; at &lt;strong data-start=&quot;154&quot; data-end=&quot;199&quot;&gt;T
 KR College of Engineering and Technology&lt;/strong&gt;\, organized by the &lt;stro
 ng data-start=&quot;218&quot; data-end=&quot;267&quot;&gt;IEEE CAS Student Branch Chapter (SBC600
 30787)&lt;/strong&gt; in association with &lt;strong data-start=&quot;288&quot; data-end=&quot;311
 &quot;&gt;CHIPIN Centre\, CDAC&lt;/strong&gt; and &lt;strong data-start=&quot;316&quot; data-end=&quot;334
 &quot;&gt;ECE Department&lt;/strong&gt;:&lt;/p&gt;\n&lt;hr data-start=&quot;337&quot; data-end=&quot;340&quot;&gt;\n&lt;h3 
 data-start=&quot;342&quot; data-end=&quot;383&quot;&gt;&lt;strong data-start=&quot;349&quot; data-end=&quot;383&quot;&gt;Da
 y 1 &amp;ndash\; 7th July 2025 (Monday)&lt;/strong&gt;&lt;/h3&gt;\n&lt;div class=&quot;_tableConta
 iner_1rjym_1&quot;&gt;\n&lt;div class=&quot;_tableWrapper_1rjym_13 group flex w-fit flex-c
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 dth)&quot; data-start=&quot;385&quot; data-end=&quot;1095&quot;&gt;\n&lt;thead data-start=&quot;385&quot; data-end=
 &quot;490&quot;&gt;\n&lt;tr data-start=&quot;385&quot; data-end=&quot;490&quot;&gt;\n&lt;th data-start=&quot;385&quot; data-en
 d=&quot;407&quot; data-col-size=&quot;sm&quot;&gt;Time&lt;/th&gt;\n&lt;th data-start=&quot;407&quot; data-end=&quot;490&quot; 
 data-col-size=&quot;md&quot;&gt;Session Details&lt;/th&gt;\n&lt;/tr&gt;\n&lt;/thead&gt;\n&lt;tbody data-star
 t=&quot;598&quot; data-end=&quot;1095&quot;&gt;\n&lt;tr data-start=&quot;598&quot; data-end=&quot;717&quot;&gt;\n&lt;td data-s
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 data-end=&quot;717&quot; data-col-size=&quot;md&quot;&gt;&lt;strong data-start=&quot;626&quot; data-end=&quot;647&quot;&gt;
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  Dean\, HoD\, IEEE Coordinator&lt;/td&gt;\n&lt;/tr&gt;\n&lt;tr data-start=&quot;718&quot; data-end=
 &quot;829&quot;&gt;\n&lt;td data-start=&quot;718&quot; data-end=&quot;744&quot; data-col-size=&quot;sm&quot;&gt;&lt;strong dat
 a-start=&quot;720&quot; data-end=&quot;743&quot;&gt;10:00 AM &amp;ndash\; 11:30 AM&lt;/strong&gt;&lt;/td&gt;\n&lt;td
  data-start=&quot;744&quot; data-end=&quot;829&quot; data-col-size=&quot;md&quot;&gt;&lt;strong data-start=&quot;74
 6&quot; data-end=&quot;760&quot;&gt;Session I:&lt;/strong&gt; Introduction to VLSI &amp;amp\; CMOS Bas
 ics &lt;br&gt;&lt;strong data-start=&quot;800&quot; data-end=&quot;812&quot;&gt;Speaker:&lt;/strong&gt; Dr. P. K
 alyani&lt;/td&gt;\n&lt;/tr&gt;\n&lt;tr data-start=&quot;830&quot; data-end=&quot;948&quot;&gt;\n&lt;td data-start=&quot;
 830&quot; data-end=&quot;856&quot; data-col-size=&quot;sm&quot;&gt;&lt;strong data-start=&quot;832&quot; data-end=&quot;
 855&quot;&gt;11:45 AM &amp;ndash\; 01:00 PM&lt;/strong&gt;&lt;/td&gt;\n&lt;td data-start=&quot;856&quot; data-e
 nd=&quot;948&quot; data-col-size=&quot;md&quot;&gt;&lt;strong data-start=&quot;858&quot; data-end=&quot;873&quot;&gt;Sessio
 n II:&lt;/strong&gt; CMOS Inverter &amp;amp\; Common Source Amplifier &lt;br&gt;&lt;strong da
 ta-start=&quot;918&quot; data-end=&quot;930&quot;&gt;Speaker:&lt;/strong&gt; Dr. B. Srikanth&lt;/td&gt;\n&lt;/tr
 &gt;\n&lt;tr data-start=&quot;949&quot; data-end=&quot;994&quot;&gt;\n&lt;td data-start=&quot;949&quot; data-end=&quot;97
 5&quot; data-col-size=&quot;sm&quot;&gt;&lt;strong data-start=&quot;951&quot; data-end=&quot;974&quot;&gt;01:00 PM &amp;nd
 ash\; 02:00 PM&lt;/strong&gt;&lt;/td&gt;\n&lt;td data-start=&quot;975&quot; data-end=&quot;994&quot; data-col
 -size=&quot;md&quot;&gt;&lt;strong data-start=&quot;977&quot; data-end=&quot;992&quot;&gt;Lunch Break&lt;/strong&gt;&lt;/t
 d&gt;\n&lt;/tr&gt;\n&lt;tr data-start=&quot;995&quot; data-end=&quot;1095&quot;&gt;\n&lt;td data-start=&quot;995&quot; dat
 a-end=&quot;1021&quot; data-col-size=&quot;sm&quot;&gt;&lt;strong data-start=&quot;997&quot; data-end=&quot;1020&quot;&gt;0
 2:00 PM &amp;ndash\; 04:30 PM&lt;/strong&gt;&lt;/td&gt;\n&lt;td data-start=&quot;1021&quot; data-end=&quot;1
 095&quot; data-col-size=&quot;md&quot;&gt;&lt;strong data-start=&quot;1023&quot; data-end=&quot;1046&quot;&gt;Hands-on
  Session I:&lt;/strong&gt; Cadence ADE &amp;ndash\; Inverter Simulation &amp;amp\; DC Bi
 asing&lt;/td&gt;\n&lt;/tr&gt;\n&lt;/tbody&gt;\n&lt;/table&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;hr data-start=&quot;109
 7&quot; data-end=&quot;1100&quot;&gt;\n&lt;h3 data-start=&quot;1102&quot; data-end=&quot;1144&quot;&gt;&lt;strong data-st
 art=&quot;1109&quot; data-end=&quot;1144&quot;&gt;Day 2 &amp;ndash\; 8th July 2025 (Tuesday)&lt;/strong&gt;
 &lt;/h3&gt;\n&lt;div class=&quot;_tableContainer_1rjym_1&quot;&gt;\n&lt;div class=&quot;_tableWrapper_1r
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 head data-start=&quot;1146&quot; data-end=&quot;1251&quot;&gt;\n&lt;tr data-start=&quot;1146&quot; data-end=&quot;1
 251&quot;&gt;\n&lt;th data-start=&quot;1146&quot; data-end=&quot;1168&quot; data-col-size=&quot;sm&quot;&gt;Time&lt;/th&gt;\
 n&lt;th data-start=&quot;1168&quot; data-end=&quot;1251&quot; data-col-size=&quot;md&quot;&gt;Session Details&lt;
 /th&gt;\n&lt;/tr&gt;\n&lt;/thead&gt;\n&lt;tbody data-start=&quot;1359&quot; data-end=&quot;1807&quot;&gt;\n&lt;tr data
 -start=&quot;1359&quot; data-end=&quot;1471&quot;&gt;\n&lt;td data-start=&quot;1359&quot; data-end=&quot;1385&quot; data
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  11:00 AM&lt;/strong&gt;&lt;/td&gt;\n&lt;td data-start=&quot;1385&quot; data-end=&quot;1471&quot; data-col-si
 ze=&quot;md&quot;&gt;&lt;strong data-start=&quot;1387&quot; data-end=&quot;1402&quot;&gt;Session IV:&lt;/strong&gt; Lay
 out Design\, DRC &amp;amp\; LVS Concepts &lt;br&gt;&lt;strong data-start=&quot;1441&quot; data-en
 d=&quot;1453&quot;&gt;Speaker:&lt;/strong&gt; Dr. B. Srikanth&lt;/td&gt;\n&lt;/tr&gt;\n&lt;tr data-start=&quot;14
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 &quot;sm&quot;&gt;&lt;strong data-start=&quot;1474&quot; data-end=&quot;1497&quot;&gt;11:15 AM &amp;ndash\; 01:00 PM&lt;
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 trong data-start=&quot;1500&quot; data-end=&quot;1514&quot;&gt;Session V:&lt;/strong&gt; Career Opportu
 nities in VLSI Industry &lt;br&gt;&lt;strong data-start=&quot;1557&quot; data-end=&quot;1569&quot;&gt;Spea
 ker:&lt;/strong&gt; Dr. P. Kalyani&lt;/td&gt;\n&lt;/tr&gt;\n&lt;tr data-start=&quot;1587&quot; data-end=&quot;
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 ize=&quot;sm&quot;&gt;&lt;strong data-start=&quot;1635&quot; data-end=&quot;1658&quot;&gt;02:00 PM &amp;ndash\; 04:30
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 &quot;&gt;&lt;strong data-start=&quot;1661&quot; data-end=&quot;1685&quot;&gt;Hands-on Session II:&lt;/strong&gt; 
 AC Analysis &amp;amp\; Layout Design in Cadence&lt;/td&gt;\n&lt;/tr&gt;\n&lt;tr data-start=&quot;1
 727&quot; data-end=&quot;1807&quot;&gt;\n&lt;td data-start=&quot;1727&quot; data-end=&quot;1753&quot; data-col-size
 =&quot;sm&quot;&gt;&lt;strong data-start=&quot;1729&quot; data-end=&quot;1749&quot;&gt;04:30 PM onwards&lt;/strong&gt;&lt;
 /td&gt;\n&lt;td data-start=&quot;1753&quot; data-end=&quot;1807&quot; data-col-size=&quot;md&quot;&gt;&lt;strong dat
 a-start=&quot;1755&quot; data-end=&quot;1805&quot;&gt;Valedictory Session &amp;amp\; Certificate Dist
 ribution&lt;/strong&gt;&lt;/td&gt;\n&lt;/tr&gt;\n&lt;/tbody&gt;\n&lt;/table&gt;\n&lt;/div&gt;\n&lt;/div&gt;
END:VEVENT
END:VCALENDAR