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VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
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TZID:America/Bogota
BEGIN:DAYLIGHT
DTSTART:20380118T221407
TZOFFSETFROM:-0500
TZOFFSETTO:-0500
RRULE:FREQ=YEARLY;BYDAY=3MO;BYMONTH=1
TZNAME:-05
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BEGIN:STANDARD
DTSTART:19930206T230000
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
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BEGIN:VEVENT
DTSTAMP:20250905T170829Z
UID:0B45EC46-F4E0-444B-87C8-DDBA5093E815
DTSTART;TZID=America/Bogota:20250901T160000
DTEND;TZID=America/Bogota:20250904T180000
DESCRIPTION:This workshop introduces participants to advanced concepts and 
 practical methodologies in FinFET layout design. The session will cover th
 e key challenges of nanoscale device integration\, design rules\, and layo
 ut techniques specific to FinFET technologies. Through a combination of th
 eoretical discussion and hands-on exercises\, students will gain practical
  skills to address parasitics\, matching strategies\, and reliability cons
 iderations in advanced nodes.\n\nSpeaker(s): Alex Mantilla \, Jeison Aceve
 do\, \n\nRoom: 150\, Bldg: Laboratorios Pesados\, carrera 27 calle 9\, Buc
 amanga\, Santander\, Colombia\, 680002
LOCATION:Room: 150\, Bldg: Laboratorios Pesados\, carrera 27 calle 9\, Buca
 manga\, Santander\, Colombia\, 680002
ORGANIZER:sergio.c@ieee.org
SEQUENCE:99
SUMMARY:Workshop on Advanced FinFET Layout – Part 1
URL;VALUE=URI:https://events.vtools.ieee.org/m/499138
X-ALT-DESC:Description: <br /><p>This workshop introduces participants to a
 dvanced concepts and practical methodologies in FinFET layout design. The 
 session will cover the key challenges of nanoscale device integration\, de
 sign rules\, and layout techniques specific to FinFET technologies. Throug
 h a combination of theoretical discussion and hands-on exercises\, student
 s will gain practical skills to address parasitics\, matching strategies\,
  and reliability considerations in advanced nodes.</p>
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