BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20251014T082749Z
UID:382D5E99-7E59-4C95-886D-B62C27F0E504
DTSTART;TZID=Asia/Kolkata:20251011T093000
DTEND;TZID=Asia/Kolkata:20251011T163000
DESCRIPTION:iChip 3.0 is a 7-hour FPGA Innovation Hackathon designed to cha
 llenge participants’ skills in Verilog coding\, debugging\, and digital 
 circuit design. Organized under CASS Convergence 2025\, this event provide
 s a hands-on platform for students to explore the journey from code to chi
 p implementation.\n\nParticipants will debug\, design\, and deploy digital
  circuits on FPGA boards\, competing in multiple challenge rounds. The hac
 kathon not only tests technical knowledge but also encourages teamwork\, c
 reativity\, and time-bound problem-solving.\n\nWith limited registrations 
 on a first-come\, first-serve basis\, the event promises intense competiti
 on\, innovation\, and exciting prizes for winners.\n\nCo-sponsored by: Cha
 rotar University of Science and Technology (CHARUSAT)\n\nRoom: Project Lab
  2\, EC Dept.\, A6 Building\, CSPIT\, Bldg: A6\, Department of Electronics
  and Communication\, Charotar University of Science and Technology (CHARUS
 AT)\, CSPIT Campus\, Off Nadiad-Petlad Highway\, Changa\, Anand\, Gujarat\
 , India\, 388421
LOCATION:Room: Project Lab 2\, EC Dept.\, A6 Building\, CSPIT\, Bldg: A6\, 
 Department of Electronics and Communication\, Charotar University of Scien
 ce and Technology (CHARUSAT)\, CSPIT Campus\, Off Nadiad-Petlad Highway\, 
 Changa\, Anand\, Gujarat\, India\, 388421
ORGANIZER:ieee.casschapter@charusat.edu.in
SEQUENCE:27
SUMMARY:iChip - 3.0 “Code2Chip: FPGA Innovation Hackathon”
URL;VALUE=URI:https://events.vtools.ieee.org/m/500280
X-ALT-DESC:Description: &lt;br /&gt;&lt;p style=&quot;text-align: justify\;&quot; data-start=&quot;
 403&quot; data-end=&quot;722&quot;&gt;&lt;strong data-start=&quot;403&quot; data-end=&quot;416&quot;&gt;iChip 3.0&lt;/str
 ong&gt; is a &lt;strong data-start=&quot;422&quot; data-end=&quot;458&quot;&gt;7-hour FPGA Innovation H
 ackathon&lt;/strong&gt; designed to challenge participants&amp;rsquo\; skills in &lt;st
 rong data-start=&quot;505&quot; data-end=&quot;562&quot;&gt;Verilog coding\, debugging\, and digi
 tal circuit design&lt;/strong&gt;. Organized under &lt;strong data-start=&quot;580&quot; data
 -end=&quot;605&quot;&gt;CASS Convergence 2025&lt;/strong&gt;\, this event provides a hands-on
  platform for students to explore the journey from &lt;strong data-start=&quot;688
 &quot; data-end=&quot;719&quot;&gt;code to chip implementation&lt;/strong&gt;.&lt;/p&gt;\n&lt;p style=&quot;text
 -align: justify\;&quot; data-start=&quot;724&quot; data-end=&quot;969&quot;&gt;Participants will debug
 \, design\, and deploy digital circuits on &lt;strong data-start=&quot;788&quot; data-e
 nd=&quot;803&quot;&gt;FPGA boards&lt;/strong&gt;\, competing in multiple challenge rounds. Th
 e hackathon not only tests technical knowledge but also encourages teamwor
 k\, creativity\, and time-bound problem-solving.&lt;/p&gt;\n&lt;p style=&quot;text-align
 : justify\;&quot; data-start=&quot;971&quot; data-end=&quot;1124&quot;&gt;With &lt;strong data-start=&quot;976
 &quot; data-end=&quot;1036&quot;&gt;limited registrations on a first-come\, first-serve basi
 s&lt;/strong&gt;\, the event promises intense competition\, innovation\, and exc
 iting prizes for winners.&lt;/p&gt;
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END:VCALENDAR