BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Chicago BEGIN:DAYLIGHT DTSTART:20250309T030000 TZOFFSETFROM:-0600 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:CDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20251102T010000 TZOFFSETFROM:-0500 TZOFFSETTO:-0600 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:CST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250929T003020Z UID:B30300A0-D270-4EE6-85BD-6274367099BC DTSTART;TZID=America/Chicago:20250926T130000 DTEND;TZID=America/Chicago:20250926T140000 DESCRIPTION:Zoom link: https://argonne.zoomgov.com/j/1602717824?pwd=NZxbKVS 1Ac24psobtx2C90Pa9Jpn2r.1\n\nSpeaker:\n\nProf. Cheng Wang\n\nDepartment of Electrical and Computer Engineering\, Iowa State University\n\nDate & Tim e:\n\nSeptember 26\, 1:00 pm - 2:00 pm\, CST\n\nAbstract:\n\nThe pursuit o f high-performance and energy-efficient computing for artificial intellige nce (AI) opens up exciting opportunities for emerging memories and unconve ntional architectures such as analog in-memory computing (IMC). To maximiz e the potential of such emerging computing technologies\, innovations acro ss the stack (from devices to systems) are needed. In this talk\, I will s hare some of our group’s recent co-design efforts in exploiting spintron ic components for developing efficient deep neural network (DNN) hardware. First\, a multi-level spintronic synaptic device based on a composite mag netic tunnel junction (MTJ) is proposed and analyzed in simulation. By int egrating a standard MTJ free layer exchange coupled with a granular magnet ic nanostructure\, multiple near-continuous nonvolatile resistive states c an be induced thanks to the distribution of the energy barrier among indiv idual magnetic grains. Second\, we exploit stochastic MTJs as the core com ponents for the array-level partial sums (PS) in crossbar architecture and for the processing engines in near-memory systolic arrays. Leveraging the probabilistic switching of spin-orbit torque (SOT) MTJs\, the proposed PS processing eliminates the costly Analog-Digital Conversion in crossbar IM C\, leading to significant improvement in energy and area efficiency. We f urther show that the accuracy loss due to quantization error can be mitiga ted by a newly developed PS-quantization-aware DNN training methodology. O ur device-to-system co-optimization research demonstrates exciting opportu nities for spintronics in developing next-generation energy-efficient inte lligent computing systems. I will conclude my talk with discussions on the potential of co-designing spintronics for various unconventional computat ional functionalities.\n\nBiography:\n\nCheng Wang is an Assistant Profess or of Electrical and Computer Engineering at Iowa State University. Cheng received his B.S. degree in physics from Peking University in 2009 and com pleted his Ph.D. from the University of Texas at Austin in 2016\, with his dissertation on exploring spintronic and memristive devices. Prior to joi ning Iowa State\, Cheng was a Research Scientist at the Center for Brain-i nspired Computing Enabling (C-BRIC) at Purdue University. Cheng worked as a Staff R&D Engineer at Seagate Research Center from 2016 to 2019\, where he designed high-density magneto-electronic memory and storage technologie s. His current research interests include machine learning hardware accele ration and energy-efficient neuromorphic computing with emerging technolog ies and architectures. He has served on the Technical Program Committee fo r beyond-CMOS and emerging technologies for IEEE/ACM Design Automation Con ference (DAC)\, International Conference on Computer-Aided Design (ICCAD)\ , and the Great Lakes Symposium on VLSI. He is a recipient of the NSF CARE ER Award\, Seagate FRC Technical Award\, and Best Paper Award for the IEEE International Conference on Rebooting Computing (ICRC).\n\nCo-sponsored b y: IEEE Chicago\, IEEE NTC Young Professionals\n\n9700 S Cass Ave\, Bldg. 222\, A229\, LEMONT\, Illinois\, United States\, 60439\, Virtual: https:// events.vtools.ieee.org/m/500597 LOCATION:9700 S Cass Ave\, Bldg. 222\, A229\, LEMONT\, Illinois\, United St ates\, 60439\, Virtual: https://events.vtools.ieee.org/m/500597 ORGANIZER:yili@anl.gov SEQUENCE:23 SUMMARY:(Sep. 26\, 2025) Enabling Energy-Efficient Artificial Intelligence Hardware with Spintronics URL;VALUE=URI:https://events.vtools.ieee.org/m/500597 X-ALT-DESC:Description: <br /><p><strong>Zoom link: </strong>https://argonn e.zoomgov.com/j/1602717824?pwd=NZxbKVS1Ac24psobtx2C90Pa9Jpn2r.1</p>\n<p><s trong>Speaker:&nbsp\;</strong></p>\n<p>Prof. Cheng Wang&nbsp\;</p>\n<p>Dep artment of Electrical and Computer Engineering\,&nbsp\;Iowa State Universi ty</p>\n<p><strong>Date &amp\; Time:</strong></p>\n<p>September 26\, 1:00 pm - 2:00 pm\, CST</p>\n<p><strong>Abstract:</strong></p>\n<p>The pursuit of high-performance and energy-efficient computing for artificial intellig ence (AI)&nbsp\;opens up exciting opportunities for emerging memories and unconventional architectures&nbsp\;such as analog in-memory computing (IMC ). To maximize the potential of such emerging&nbsp\;computing technologies \, innovations across the stack (from devices to systems) are&nbsp\;needed . In this talk\, I will share some of our group&rsquo\;s recent co-design efforts in exploiting&nbsp\;spintronic components for developing efficient deep neural network (DNN) hardware. First\,&nbsp\;a multi-level spintroni c synaptic device based on a composite magnetic tunnel junction&nbsp\;(MTJ ) is proposed and analyzed in simulation. By integrating a standard MTJ fr ee layer&nbsp\;exchange coupled with a granular magnetic nanostructure\, m ultiple near-continuous nonvolatile resistive states can be induced thanks to the distribution of the energy barrier among&nbsp\;individual magnetic grains. Second\, we exploit stochastic MTJs as the core components for&nb sp\;the array-level partial sums (PS) in crossbar architecture and for the processing engines in&nbsp\;near-memory systolic arrays. Leveraging the p robabilistic switching of spin-orbit torque&nbsp\;(SOT) MTJs\, the propose d PS processing eliminates the costly Analog-Digital Conversion in&nbsp\;c rossbar IMC\, leading to significant improvement in energy and area effici ency. We further&nbsp\;show that the accuracy loss due to quantization err or can be mitigated by a newly developed&nbsp\;PS-quantization-aware DNN t raining methodology. Our device-to-system co-optimization&nbsp\;research d emonstrates exciting opportunities for spintronics in developing next-gene ration&nbsp\;energy-efficient intelligent computing systems. I will conclu de my talk with discussions on the potential of co-designing spintronics f or various unconventional computational&nbsp\;functionalities.</p>\n<p>&nb sp\;</p>\n<p><strong data-olk-copy-source="MessageBody">Biography:</strong ></p>\n<p>Cheng Wang is an Assistant Professor of Electrical and Computer Engineering at Iowa State University. Cheng received his B.S. degree in ph ysics from Peking University in 2009 and completed his Ph.D. from the Univ ersity of Texas at Austin in 2016\, with his dissertation on exploring spi ntronic and memristive devices. Prior to joining Iowa State\, Cheng was a Research Scientist at the Center for Brain-inspired Computing Enabling (C- BRIC) at Purdue University. Cheng worked as a Staff R&amp\;D Engineer at S eagate Research Center from 2016 to 2019\, where he designed high-density magneto-electronic memory and storage technologies. His current research i nterests include machine learning hardware acceleration and energy-efficie nt neuromorphic computing with emerging technologies and architectures. He has served on the Technical Program Committee for beyond-CMOS and emergin g technologies for IEEE/ACM Design Automation Conference (DAC)\, Internati onal Conference on Computer-Aided Design (ICCAD)\, and the Great Lakes Sym posium on VLSI. He is a recipient of the NSF CAREER Award\, Seagate FRC Te chnical Award\, and Best Paper Award for the IEEE International Conference on Rebooting Computing (ICRC).</p> END:VEVENT END:VCALENDAR