BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20250309T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20251102T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250912T075343Z UID:E94C2423-DD8A-4604-8E93-9FA6BB85DF6A DTSTART;TZID=America/Los_Angeles:20250925T180000 DTEND;TZID=America/Los_Angeles:20250925T200000 DESCRIPTION:Speaker: Dr. Boris Vaisband\n\nMeeting Date: September 25th\, 2 025\n6:00 - 7:00pm Check in and Network\n7:00 - 8:00pm Presentation\n\nAbs tract\nThe demand for computation and memory in applications such as large language models\, has increased well beyond the reticle boundaries of a s ystem-on-chip (SoC). Chiplet-based integration is a paradigm shift that sh apes the way we design our future high-performance systems. The concept is to move away from large SoCs that are limited by communication\, thermal design power\, and reticle size\, toward a robust plug-and-play approach\, where small\, hardened IP heterogeneous off-the-shelf chiplets are seamle ssly integrated on a single platform. In this talk\, we will discuss the c urrent state-of-the-art and challenges in chiplet integration and introduc e the silicon interconnect fabric (Si-IF)\, an ultra-large wafer-scale het erogeneous integration platform\, for applications such as artificial inte lligence acceleration\, high-performance computing\, and neuromorphic hard ware\, will be discussed.\n\nBio\n\nBoris Vaisband (Senior Member\, IEEE) is the Samueli Development Chair Assistant Professor at the University of California\, Irvine\, working on heterogeneous systems integration. In 202 4 he was the Acting Director of UCLA CHIPS\, and from 2019 to 2024\, an As sistant Professor at McGill University. He received a B.S. degree in Compu ter Engineering from the Technion – Israel Institute of Technology in 20 11\, and M.S. and Ph.D. degrees in Electrical Engineering from the Univers ity of Rochester\, NY\, in\, respectively\, 2012 and 2017. From 2017 to 20 19\, he was a Postdoctoral Scholar at UCLA. From 2008 to 2015\, he held va rious hardware design positions at Intel\, Cisco\, and Google. His current research interests are in heterogeneous integration\, advanced packaging\ , and neuromorphic systems\, with a focus on circuits\, EDA tools\, and de sign methodologies for power delivery\, communication\, thermal aware desi gn and floorplanning\, and testing. Some applications of interest are ultr a-large-scale artificial intelligence systems and high performance computi ng.\n\nBldg: Building#1\, Broadcom\, 15101 Alton Parkway\, Irvine\, Calif ornia\, United States\, 92618 LOCATION:Bldg: Building#1\, Broadcom\, 15101 Alton Parkway\, Irvine\, Cali fornia\, United States\, 92618 ORGANIZER:hichrih@ajiusa.com SEQUENCE:18 SUMMARY:Chiplet-Based Heterogeneous Integration for Ultra-Large-Scale Appli cations URL;VALUE=URI:https://events.vtools.ieee.org/m/500683 X-ALT-DESC:Description: <br /><p><strong>Speaker: Dr. Boris Vaisband</stron g></p>\n<p><strong>Meeting Date: September 25th\, 2025</strong></p>\n<div dir="auto">6:00 - 7:00pm Check in and Network</div>\n<div dir="auto">7:00 - 8:00pm Presentation</div>\n<div dir="auto">&nbsp\;</div>\n<p><strong>Abs tract</strong><br>The demand for computation and memory in applications su ch as large language models\, has increased well beyond the reticle bounda ries of a system-on-chip (SoC). Chiplet-based integration is a paradigm sh ift that shapes the way we design our future high-performance systems. The concept is to move away from large SoCs that are limited by communication \, thermal design power\, and reticle size\, toward a robust plug-and-play approach\, where small\, hardened IP heterogeneous off-the-shelf chiplets are seamlessly integrated on a single platform. In this talk\, we will di scuss the current state-of-the-art and challenges in chiplet integration a nd introduce the silicon interconnect fabric (Si-IF)\, an ultra-large wafe r-scale heterogeneous integration platform\, for applications such as arti ficial intelligence acceleration\, high-performance computing\, and neurom orphic hardware\, will be discussed.</p>\n<p>&nbsp\;</p>\n<div><strong>Bio </strong></div>\n<p>Boris Vaisband (Senior Member\, IEEE) is the Samueli D evelopment Chair Assistant Professor at the University of California\, Irv ine\, working on heterogeneous systems integration. In 2024 he was the Act ing Director of UCLA CHIPS\, and from 2019 to 2024\, an Assistant Professo r at McGill University. He received a B.S. degree in Computer Engineering from the Technion &ndash\; Israel Institute of Technology in 2011\, and M. S. and Ph.D. degrees in Electrical Engineering from the University of Roch ester\, NY\, in\, respectively\, 2012 and 2017. From 2017 to 2019\, he was a Postdoctoral Scholar at UCLA. From 2008 to 2015\, he held various hardw are design positions at Intel\, Cisco\, and Google. His current research i nterests are in heterogeneous integration\, advanced packaging\, and neuro morphic systems\, with a focus on circuits\, EDA tools\, and design method ologies for power delivery\, communication\, thermal aware design and floo rplanning\, and testing. Some applications of interest are ultra-large-sca le artificial intelligence systems and high performance computing.</p> END:VEVENT END:VCALENDAR