BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:America/Sao_Paulo
BEGIN:DAYLIGHT
DTSTART:20380119T001407
TZOFFSETFROM:-0300
TZOFFSETTO:-0300
RRULE:FREQ=YEARLY;BYDAY=3TU;BYMONTH=1
TZNAME:-03
END:DAYLIGHT
BEGIN:STANDARD
DTSTART:20190216T230000
TZOFFSETFROM:-0200
TZOFFSETTO:-0300
RRULE:FREQ=YEARLY;BYDAY=3SA;BYMONTH=2
TZNAME:-03
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20251119T215741Z
UID:FA3063AA-982B-4A80-A44A-D1C87D5FA20F
DTSTART;TZID=America/Sao_Paulo:20250926T100000
DTEND;TZID=America/Sao_Paulo:20250926T110000
DESCRIPTION:Charge capture and emission by defects (traps) close to the Die
 lectric-Semiconductor interface is the major source of low-frequency noise
  in modern MOS devices. It also causes Bias Temperature Instability (BTI).
  The mechanisms involved in charge trapping are presented\, including a cr
 itical discussion of key parameters such as trapping/de-trapping time cons
 tants and the amplitude of the fluctuations induced by single traps. A nov
 el physics-based modeling and simulation approach for BTI\, RTN and 1/f no
 ise is presented. It allows for the derivation of analytical formulations 
 for 1/f noise (frequency domain) and RTN (time domain) using a single mode
 ling framework\, where model parameters are the same in frequency and time
  domain. Low Frequency Noise (and BTI) levels can vary by several orders o
 f magnitude in deeply scaled devices\, making variability a major concern 
 in advanced MOS technologies. To ensure proper circuit design in this scen
 ario\, it is necessary to identify the fundamental mechanisms responsible 
 for variability in noise and BTI. Time domain analysis is relevant for the
  analysis of digital and mixed-signal circuits. In digital circuits\, the 
 RTN chronological statistics\, especially trap occupancy switching\, have 
 direct impacts on circuit performance and reliability\, as degradations li
 ke jitter of signals happen when a trap switches state. The area scaling o
 f RTN induced jitter (phase noise) and its variability is detailed and dis
 cussed\, aiming to support circuit designers in transistor sizing towards 
 a more reliable design. The applicability of the model here presented to t
 he evaluation of logic gates and circuits is demonstrated by case studies.
 \n\nSpeaker(s): Gilson Wirth\n\nVirtual: https://events.vtools.ieee.org/m/
 501629
LOCATION:Virtual: https://events.vtools.ieee.org/m/501629
ORGANIZER:sandro.b.ferreira@ieee.org
SEQUENCE:18
SUMMARY:EDS DISTINGUISHED LECTURE - Webinar - Charge Trapping in Semiconduc
 tor Devices - Prof. Gilson I Wirth
URL;VALUE=URI:https://events.vtools.ieee.org/m/501629
X-ALT-DESC:Description: <br /><p style="language: pt-BR\; line-height: norm
 al\; text-indent: 0in\; text-align: justify\; text-justify: inter-ideograp
 h\; direction: ltr\; unicode-bidi: embed\; margin: 0pt 0in 0pt 0in\;"><spa
 n style="font-size: 10pt\; font-family: Calibri\; font-variant: normal\; c
 olor: black\; text-transform: none\; font-weight: normal\; font-style: nor
 mal\;">Charge capture and emission by defects (traps) close to the Dielect
 ric-Semiconductor interface is the major source of low-frequency noise in 
 modern MOS devices. It also causes Bias Temperature Instability (BTI). The
  mechanisms involved in charge trapping are presented\, including a critic
 al discussion of key parameters such as trapping/de-trapping time constant
 s and the amplitude of the fluctuations induced by single traps. A novel p
 hysics-based modeling and simulation approach for BTI\, RTN and 1/f noise 
 is presented. It allows for the derivation of analytical formulations for 
 1/f noise (frequency domain) and RTN (time domain) using a single modeling
  framework\, where model parameters are the same in frequency and time dom
 ain.<span style="mso-spacerun: yes\;">&nbsp\; </span>Low Frequency Noise (
 and BTI) levels can vary by several orders of magnitude in deeply scaled d
 evices\, making variability a major concern in advanced MOS technologies. 
 To ensure proper circuit design in this scenario\, it is necessary to iden
 tify the fundamental mechanisms responsible for variability in noise and B
 TI. Time domain analysis is relevant for the analysis of digital and mixed
 -signal circuits.<span style="mso-spacerun: yes\;">&nbsp\; </span>In digit
 al circuits\, the RTN chronological statistics\, especially trap occupancy
  switching\, have direct impacts on circuit performance and reliability\, 
 as degradations like jitter of signals happen when a trap switches state. 
 The area scaling of RTN induced jitter (phase noise) and its variability i
 s detailed and discussed\, aiming to support circuit designers in transist
 or sizing towards a more reliable design. The applicability of the model h
 ere presented to the evaluation of logic gates and circuits is demonstrate
 d by case studies.</span></p>
END:VEVENT
END:VCALENDAR