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DTSTART:20260308T030000
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DTSTART:20251102T010000
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DTSTAMP:20251211T205525Z
UID:D37B1F9F-DCF4-4B9C-A17B-455B93A5B93A
DTSTART;TZID=America/Los_Angeles:20251211T120000
DTEND;TZID=America/Los_Angeles:20251211T125500
DESCRIPTION:[]\n\nRequirements on the high-performance compute (HPC) system
 s from AI workloads necessitates transition to larger package sizes with 2
 .5D to 3.5D integration and density scaling at every level in the stack. S
 everal competing packaging architectures are emerging to solve the compute
  and power efficiency challenge presented by AI workloads. Each presents u
 nique lithography challenges such as &gt;100×100 field size\, large chip pla
 cement deviations\, fine lines and tight overlay warped substrates. The co
 nventional lithography tools are incapable of meeting all the requirements
  to achieve scaling.\n\nThe talk will preview Applied Materials’ Digital
  Lithography Technology (DLT) which enables highest resolution at producti
 on throughputs while ensuring CD uniformity and overlay accuracy across th
 e entire panel.\n\nSpeaker(s): Niranjan Khasgiwale\, \n\nVirtual: https://
 events.vtools.ieee.org/m/502777
LOCATION:Virtual: https://events.vtools.ieee.org/m/502777
ORGANIZER:p.wesling@ieee.org
SEQUENCE:22
SUMMARY:Digital Lithography: Addressing Scaling Challenges in Advanced Pack
 aging
URL;VALUE=URI:https://events.vtools.ieee.org/m/502777
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;&lt;img style=&quot;float: right\;&quot; src=&quot;https://e
 vents.vtools.ieee.org/vtools_ui/media/display/30b9926b-0798-4e5b-9e12-130b
 f5f98dbd&quot; alt=&quot;&quot; width=&quot;500&quot; height=&quot;250&quot;&gt;&lt;/p&gt;\n&lt;p&gt;Requirements on the hig
 h-performance compute (HPC) systems from AI workloads necessitates transit
 ion to larger package sizes with 2.5D to 3.5D integration and density scal
 ing at every level in the stack. Several competing packaging architectures
  are emerging to solve the compute and power efficiency challenge presente
 d by AI workloads. Each presents unique lithography challenges such as &amp;gt
 \;100&amp;times\;100 field size\, large chip placement deviations\, fine lines
  and tight overlay warped substrates. The conventional lithography tools a
 re incapable of meeting all the requirements to achieve scaling.&lt;/p&gt;\n&lt;p&gt;T
 he talk will preview Applied Materials&amp;rsquo\; Digital Lithography Technol
 ogy (DLT) which enables highest resolution at production throughputs while
  ensuring CD uniformity and overlay accuracy across the entire panel.&amp;nbsp
 \;&lt;/p&gt;
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