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DTSTAMP:20251011T085926Z
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DTSTART;TZID=America/Los_Angeles:20251002T173000
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DESCRIPTION:Technical talk with the following abstract:\n\nDespite the much
  debated end of Moore's Law\, CMOS scaling still maintains economic releva
 nce with 3nm finFET SoCs already in the marketplace for three years and 2n
 m gate-all-around SoCs anticipated late this year. Area scaling extensivel
 y driven by design/technology innovations co-optimized for primarily logic
  scaling continue to offer compelling node-to-node power\, performance\, a
 rea\, and cost benefits. In this tutorial\, we will start with a walk thro
 ugh memory lane\, recounting a brief history of transistor evolution to mo
 tivate the migration from the planar MOSFET to the fully depleted FinFET. 
 We will summarize the key process technology elements that have enabled th
 e finFET CMOS nodes\, highlighting the resulting device technology charact
 eristics and challenges. This will set the context for motivating the tran
 sition to the gate-all-around device architecture\, namely nanoribbons or 
 nanosheets\, and unveiling the magic of how these devices are fabricated.\
 n\nSpeaker(s): Alvin Loke\, \n\nRoom: CEME 1202\, Bldg: Civil and Mechanic
 al Engineering Building\, 6250 Applied Science Lane\, Vancouver\, British 
 Columbia\, Canada\, V6T 1Z4
LOCATION:Room: CEME 1202\, Bldg: Civil and Mechanical Engineering Building\
 , 6250 Applied Science Lane\, Vancouver\, British Columbia\, Canada\, V6T 
 1Z4
ORGANIZER:sudip@ece.ubc.ca; htalaeia@student.ubc.ca; shahriar@ece.ubc.ca
SEQUENCE:3
SUMMARY:The Road to Gate-All-Around CMOS
URL;VALUE=URI:https://events.vtools.ieee.org/m/503056
X-ALT-DESC:Description: <br /><p>Technical talk with the following abstract
 :</p>\n<p>Despite the much debated end of Moore's Law\, CMOS scaling still
  maintains economic relevance with 3nm finFET SoCs already in the marketpl
 ace for three years and 2nm gate-all-around SoCs anticipated late this yea
 r. Area scaling extensively driven by design/technology innovations co-opt
 imized for primarily logic scaling continue to offer compelling node-to-no
 de power\, performance\, area\, and cost benefits. In this tutorial\, we w
 ill start with a walk through memory lane\, recounting a brief history of 
 transistor evolution to motivate the migration from the planar MOSFET to t
 he fully depleted FinFET. We will summarize the key process technology ele
 ments that have enabled the finFET CMOS nodes\, highlighting the resulting
  device technology characteristics and challenges. This will set the conte
 xt for motivating the transition to the gate-all-around device architectur
 e\, namely nanoribbons or nanosheets\, and unveiling the magic of how thes
 e devices are fabricated.</p>
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