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BEGIN:VTIMEZONE
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TZOFFSETFROM:-0500
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RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3
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DTSTART:20251102T010000
TZOFFSETFROM:-0400
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RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11
TZNAME:EST
END:STANDARD
END:VTIMEZONE
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DTSTAMP:20251029T163823Z
UID:6F87EC7F-3567-4565-8666-5DAFD30AA474
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DTEND;TZID=America/New_York:20251029T100000
DESCRIPTION:[]\n\nAbstract: In an era where sustainability is essential\, d
 esigning low-power integrated circuits (ICs) plays a crucial role in reduc
 ing energy consumption and mitigating environmental impact. This talk exam
 ines innovative strategies in low-power IC design to meet the increasing d
 emand for energy-efficient electronics\, from IoT devices to large-scale c
 omputing systems. By utilizing advanced techniques such as subthreshold op
 eration\, power gating\, clock gating\, and dynamic voltage scaling\, we o
 utline a framework for optimizing performance while minimizing power dissi
 pation. The discussion emphasizes the interplay between circuit-level inno
 vations\, such as the strategic use of clock gating to reduce dynamic powe
 r in idle states\, process technology advancements\, and system-level inte
 gration\, highlighting their collective contribution to sustainability. Th
 rough simulations and case studies\, we demonstrate how these approaches c
 an significantly lower the carbon footprint of electronic systems\, paving
  the way for greener technology solutions that align with global sustainab
 ility goals.\n\nSpeaker(s): Victor\, \n\nRoom: 260\, Bldg: Dreese Lab\, De
 partment of Electrical and Computer Engineering\, 2015 Neil Avenue\, Colum
 bus\, Ohio\, United States\, 43210\, Virtual: https://events.vtools.ieee.o
 rg/m/503099
LOCATION:Room: 260\, Bldg: Dreese Lab\, Department of Electrical and Comput
 er Engineering\, 2015 Neil Avenue\, Columbus\, Ohio\, United States\, 4321
 0\, Virtual: https://events.vtools.ieee.org/m/503099
ORGANIZER:pberger@ieee.org
SEQUENCE:40
SUMMARY:IEEE EDS/PHO Columbus DL Speaker: Low Power IC Design for a Sustain
 able World (Victor Grimblatt\, Ph.D.\, Synopsys Chile Innovation Center)
URL;VALUE=URI:https://events.vtools.ieee.org/m/503099
X-ALT-DESC:Description: <br /><p class="MsoNormal"><strong><span style="fon
 t-size: 12.0pt\; color: black\;"><img src="https://events.vtools.ieee.org/
 vtools_ui/media/display/886021b1-efbe-4bd0-93a9-07a090a5b092" alt="" width
 ="901" height="1166"></span></strong></p>\n<p class="MsoNormal"><strong><s
 pan style="font-size: 12.0pt\; color: black\;">Abstract</span></strong><sp
 an style="font-size: 12.0pt\; color: black\;">: In an era where sustainabi
 lity is essential\, designing low-power integrated circuits (ICs) plays a 
 crucial role in reducing energy consumption and mitigating environmental i
 mpact. This talk examines innovative strategies in low-power IC design to 
 meet the increasing demand for energy-efficient electronics\, from IoT dev
 ices to large-scale computing systems. By utilizing advanced techniques su
 ch as subthreshold operation\, power gating\, clock gating\, and dynamic v
 oltage scaling\, we outline a framework for optimizing performance while m
 inimizing power dissipation. The discussion emphasizes the interplay betwe
 en circuit-level innovations\, such as the strategic use of clock gating t
 o reduce dynamic power in idle states\, process technology advancements\, 
 and system-level integration\, highlighting their collective contribution 
 to sustainability. Through simulations and case studies\, we demonstrate h
 ow these approaches can significantly lower the carbon footprint of electr
 onic systems\, paving the way for greener technology solutions that align 
 with global sustainability goals.</span></p>
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