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DESCRIPTION:Rethinking Chip Design to deliver Faster\, Smarter\, More Compa
 ct Solutions\n\n[]\n\nAbstract:\n\nCDimension is rethinking chip design fr
 om the ground up\, delivering solutions that are faster\, smarter\, and mo
 re compact.\n\nWe’re moving beyond the limitations of traditional techno
 logy.\n\nOur foundational innovations in advanced materials and semiconduc
 tor integration unlock unprecedented gains in performance\, efficiency\, a
 nd scalability – ranging from 10x to 1\,000x times greater than current 
 approaches.\n\nOur first milestone: the commercial release of ultra-thin 2
 D semiconductor materials — a foundational step toward our vision of ver
 tically integrated systems that unify compute\, memory\, and power.\n\n[]\
 n\n[]\n\nSpeaker:\n\nDr. Jiadi Zhu\n\nCEO\n\nCDimension\n\nJiadi Zhu is th
 e CEO and founder of CDimension\, a company rethinking chip design to deli
 ver faster\, smarter\, more compact solutions for the most demanding and c
 omplex computing workloads. His vision is to redefine how chips are design
 ed\, not just for higher performance\, but for fundamentally better struct
 ure and efficiency.\n\nJiadi’s technical foundation spans over a decade 
 of work at the frontier of 2D materials\, monolithic 3D integration\, and 
 device scaling. He earned his Ph.D. in Electrical Engineering from the Mas
 sachusetts Institute of Technology and has been recognized across both aca
 demia and industry for his originality in device design\, novel semiconduc
 tor materials\, and integration.\n\nHis research–from MIT to the lab ben
 ch of CDimension–has focused on how to break architectural bottlenecks t
 hrough physics-aware\, layout-driven design. Jiadi’s research has been w
 idely cited in the field and published and presented in top-tier journals 
 and conferences\, including Nature Nanotechnology and IEEE’s Internation
 al Electron Devices Meeting.\n\nJiadi’s transition from research into st
 artup leadership has drawn attention from leaders in semiconductors\, high
 -performance computing\, and next-generation AI hardware. Today\, under Ji
 adi’s leadership\, CDimension is overcoming the limitations of tradition
 al chip architectures and delivering significantly better performance\, ef
 ficiency\, and scalability across modern computing environments.\n\nAGENDA
 :\n\nThursday November 13\, 2025\n\n11:30 AM: Networking\, Pizza &amp; Drinks\
 n\nNoon -- 1 pm: Seminar\n\nPlease register on Eventbrite before 9:30 AM o
 n Thursday November 13\, 2025\n\n$4 IEEE members $6 non IEEE members\n\n(d
 iscounts for unemployed and students )\n\nSee examplesAdd\n\nCo-sponsored 
 by: 636940-Santa Clara Valley Section Chapter\,EMB18\n\nBldg: ==&gt; Use corn
 er entrance: Kifer Road / San Lucar Court ==&gt; Do not enter at main entranc
 e on Kifer Road\, EAG Labs\, 810 Kifer Road\, Sunnyvale\, California\, Cal
 ifornia\, United States\, 95051
LOCATION:Bldg: ==&gt; Use corner entrance: Kifer Road / San Lucar Court ==&gt; Do
  not enter at main entrance on Kifer Road\, EAG Labs\, 810 Kifer Road\, Su
 nnyvale\, California\, California\, United States\, 95051
ORGANIZER:G.M.Friedman@ieee.org
SEQUENCE:29
SUMMARY:Rethinking Chip Design to deliver Faster\, Smarter\, More Compact S
 olutions
URL;VALUE=URI:https://events.vtools.ieee.org/m/504128
X-ALT-DESC:Description: &lt;br /&gt;&lt;div class=&quot;eds-l-mar-vert-6 eds-l-sm-mar-ver
 t-4 eds-text-bm structured-content-rich-text&quot;&gt;\n&lt;div class=&quot;eds-text--left
 &quot;&gt;\n&lt;h1 class=&quot;event-title css-0&quot;&gt;&lt;strong&gt;Rethinking Chip Design to delive
 r Faster\, Smarter\, More Compact Solutions&lt;/strong&gt;&lt;/h1&gt;\n&lt;p&gt;&lt;img src=&quot;ht
 tps://events.vtools.ieee.org/vtools_ui/media/display/e7d14c67-114d-425b-a3
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 bstract:&lt;/strong&gt;&lt;/p&gt;\n&lt;h3&gt;CDimension is rethinking chip design from the g
 round up\, delivering solutions that are faster\, smarter\, and more compa
 ct.&lt;/h3&gt;\n&lt;h3&gt;We&amp;rsquo\;re moving beyond the limitations of traditional te
 chnology.&lt;/h3&gt;\n&lt;h3&gt;Our foundational innovations in advanced materials and
  semiconductor integration unlock unprecedented gains in performance\, eff
 iciency\, and scalability &amp;ndash\; ranging from 10x to 1\,000x times great
 er than current approaches.&lt;/h3&gt;\n&lt;h3&gt;Our first milestone: the commercial 
 release of ultra-thin 2D semiconductor materials &amp;mdash\; a foundational s
 tep toward our vision of vertically integrated systems that unify compute\
 , memory\, and power.&lt;/h3&gt;\n&lt;p&gt;&amp;nbsp\;&lt;/p&gt;\n&lt;p&gt;&lt;img src=&quot;https://events.vt
 ools.ieee.org/vtools_ui/media/display/df93fc39-3dc7-46ef-81e5-e03a2e650229
 &quot; alt=&quot;&quot; width=&quot;585&quot; height=&quot;413&quot;&gt;&lt;/p&gt;\n&lt;p&gt;&lt;img src=&quot;https://events.vtools
 .ieee.org/vtools_ui/media/display/07f63c36-fa37-4ee5-95f3-75e298709a0d&quot; al
 t=&quot;&quot; width=&quot;936&quot; height=&quot;460&quot;&gt;&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;Speaker:&lt;/strong&gt;&lt;/p&gt;\n&lt;h1&gt;
 Dr. Jiadi Zhu&lt;/h1&gt;\n&lt;h3&gt;CEO&lt;/h3&gt;\n&lt;h3&gt;CDimension&lt;/h3&gt;\n&lt;h3&gt;Jiadi Zhu is th
 e CEO and founder of CDimension\, a company rethinking chip design to deli
 ver faster\, smarter\, more compact solutions for the most demanding and c
 omplex computing workloads. His vision is to redefine how chips are design
 ed\, not just for higher performance\, but for fundamentally better struct
 ure and efficiency.&lt;br&gt;&lt;br&gt;Jiadi&amp;rsquo\;s technical foundation spans over 
 a decade of work at the frontier of 2D materials\, monolithic 3D integrati
 on\, and device scaling. He earned his Ph.D. in Electrical Engineering fro
 m the Massachusetts Institute of Technology and has been recognized across
  both academia and industry for his originality in device design\, novel s
 emiconductor materials\, and integration.&lt;br&gt;&lt;br&gt;His research&amp;ndash\;from 
 MIT to the lab bench of CDimension&amp;ndash\;has focused on how to break arch
 itectural bottlenecks through physics-aware\, layout-driven design. Jiadi&amp;
 rsquo\;s research has been widely cited in the field and published and pre
 sented in top-tier journals and conferences\, including Nature Nanotechnol
 ogy and IEEE&amp;rsquo\;s International Electron Devices Meeting.&lt;br&gt;&lt;br&gt;Jiadi
 &amp;rsquo\;s transition from research into startup leadership has drawn atten
 tion from leaders in semiconductors\, high-performance computing\, and nex
 t-generation AI hardware. Today\, under Jiadi&amp;rsquo\;s leadership\, CDimen
 sion is overcoming the limitations of traditional chip architectures and d
 elivering significantly better performance\, efficiency\, and scalability 
 across modern computing environments.&lt;/h3&gt;\n&lt;p&gt;&amp;nbsp\;&lt;/p&gt;\n&lt;h3&gt;&lt;strong&gt;AG
 ENDA:&lt;/strong&gt;&lt;/h3&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;div class=&quot;eds-l-mar-vert-6 eds-l-sm
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  13&lt;/strong&gt;&lt;strong&gt;\, 2025&lt;/strong&gt;&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;11:30 AM: Networking\
 , Pizza &amp;amp\; Drinks&lt;/strong&gt;&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;Noon -- 1 pm: Seminar&lt;/stro
 ng&gt;&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;Please register on Eventbrite before 9:30 AM on&lt;/stron
 g&gt;&lt;strong&gt; Thursday November 13\, 2025&lt;/strong&gt;&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;$4 IEEE me
 mbers&amp;nbsp\; $6 non IEEE members &lt;/strong&gt;&lt;/p&gt;\n&lt;p&gt;&lt;strong&gt;(discounts for 
 unemployed and students&lt;/strong&gt; )&lt;/p&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/div&gt;\n&lt;/
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