BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20250309T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20251102T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20251118T091046Z UID:5A9F5BEA-F5E7-4FCD-A607-D7892A2F8EDE DTSTART;TZID=America/Los_Angeles:20251016T130000 DTEND;TZID=America/Los_Angeles:20251016T140000 DESCRIPTION:Technical seminar with the following abstract:\n\nFuture data-i ntensive workloads\, particularly from artificial intelligence\, have push ed conventional computing architectures to their limits of energy efficien cy and throughput\, due to the scale of both computations and data they in volve. In- and near-memory computing are breakthrough paradigms that provi de approaches for overcoming this. But\, in doing so\, they instate new fu ndamental tradeoffs that span the device\, circuit\, and architectural lev els. This presentation starts by describing the methods by which in/near-m emory computing derive their gains\, and then examines the critical tradeo ffs\, looking concretely at recent designs across memory technologies (SRA M\, RRAM\, MRAM). Then\, its focus turns to key architectural consideratio ns\, and how these are likely to drive future technological needs and appl ication alignments. Finally\, this presentation analyzes the potential for leveraging application-level relaxations (e.g.\, noise sensitivity) throu gh algorithmic approaches.\n\nSpeaker(s): Naveen Verma\, \n\nRoom: MCLD 30 38\, Bldg: MacLeod Building\, 2356 Main Mall\, Vancouver\, British Columbi a\, Canada\, V6T 1Z4 LOCATION:Room: MCLD 3038\, Bldg: MacLeod Building\, 2356 Main Mall\, Vancou ver\, British Columbia\, Canada\, V6T 1Z4 ORGANIZER:shahriar@ece.ubc.ca SEQUENCE:16 SUMMARY:Prospects of In- and Near-Memory Computing for Future AI Systems URL;VALUE=URI:https://events.vtools.ieee.org/m/505475 X-ALT-DESC:Description: <br /><p>Technical seminar with the following abstr act:</p>\n<p class="MsoNormal"><span lang="EN-US">Future data-intensive wo rkloads\, particularly from artificial intelligence\, have pushed conventi onal computing architectures to their limits of energy efficiency and thro ughput\, due to the scale of both computations and data they involve. In- and near-memory computing are breakthrough paradigms that provide approach es for overcoming this. But\, in doing so\, they instate new fundamental t radeoffs that span the device\, circuit\, and architectural levels. This p resentation starts by describing the methods by which in/near-memory compu ting derive their gains\, and then examines the critical tradeoffs\, looki ng concretely at recent designs across memory technologies (SRAM\, RRAM\, MRAM). Then\, its focus turns to key architectural considerations\, and ho w these are likely to drive future technological needs and application ali gnments. Finally\, this presentation analyzes the potential for leveraging application-level relaxations (e.g.\, noise sensitivity) through algorith mic approaches. </span></p> END:VEVENT END:VCALENDAR