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PRODID:IEEE vTools.Events//EN
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TZID:Asia/Taipei
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DTSTART:19790930T230000
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DTSTAMP:20251008T075758Z
UID:1774220E-2813-43DB-B582-1AE7EAFFBCAE
DTSTART;TZID=Asia/Taipei:20251008T103000
DTEND;TZID=Asia/Taipei:20251010T113000
DESCRIPTION:The slowing of Moore’s Law\, the persistence of von Neumann b
 ottlenecks\, and the massive data demands of emerging applications such as
  AI call for new architectures that address both performance and sustainab
 ility. My research explores processing-in-memory (PIM) as a solution space
  to reduce data movement costs and improve efficiency\, either replacing o
 r supplementing accelerators. Using commodity DRAM as an exemplar\, we dev
 eloped a technology-agnostic PIM approach for multiplication and addition 
 that achieves up to 10× speedup and 8× higher energy efficiency over pri
 or in-DRAM proposals. With more advanced memories such as spintronic racet
 rack memory\, we leverage transverse access to construct polymorphic multi
 -input gates for multi-operand logic\, delivering up to 6.9× performance 
 and 5.5× energy gains. Extending this to floating-point operations enable
 s deep-learning acceleration at the edge\, supporting both inference and t
 raining with ≥2× efficiency compared to FPGA accelerators. We further s
 how that PIM-based solutions can outperform GPUs in reducing greenhouse ga
 s emissions\, underscoring new tradeoffs in sustainable edge AI system des
 ign. This work also reflects the broader opportunities at Syracuse Univers
 ity\, where the EECS department is building on strengths in AI\, wireless 
 communications\, and quantum systems to tackle critical technological chal
 lenges.\n\nTainan City\, T'ai-wan\, Taiwan\, 70101
LOCATION:Tainan City\, T'ai-wan\, Taiwan\, 70101
ORGANIZER:ccho@gs.ncku.edu.tw
SEQUENCE:3
SUMMARY:Moore Scaling\, Von Neumann Problems
URL;VALUE=URI:https://events.vtools.ieee.org/m/505811
X-ALT-DESC:Description: <br /><p class="MsoNormal"><span lang="EN-US"><span
  style="font-family: Arial\, sans-serif\;">The slowing of Moore&rsquo\;s L
 aw\, the persistence of von Neumann bottlenecks\, and the massive data dem
 ands of emerging applications such as AI call for new architectures that a
 ddress both performance and sustainability. My research explores processin
 g-in-memory (PIM) as a solution space to reduce data movement costs and im
 prove efficiency\, either replacing or supplementing accelerators. Using c
 ommodity DRAM as an exemplar\, we developed a technology-agnostic PIM appr
 oach for multiplication and addition that achieves up to 10&times\; speedu
 p and 8&times\; higher energy efficiency over prior in-DRAM proposals. Wit
 h more advanced memories such as spintronic racetrack memory\, we leverage
  transverse access to construct polymorphic multi-input gates for multi-op
 erand logic\, delivering up to 6.9&times\; performance and 5.5&times\; ene
 rgy gains. Extending this to floating-point operations enables deep-learni
 ng acceleration at the edge\, supporting both inference and training with 
 &ge\;2&times\; efficiency compared to FPGA accelerators. We further show t
 hat PIM-based solutions can outperform GPUs in reducing greenhouse gas emi
 ssions\, underscoring new tradeoffs in sustainable edge AI system design. 
 This work also reflects the broader opportunities at Syracuse University\,
  where the EECS department is building on strengths in AI\, wireless commu
 nications\, and quantum systems to tackle critical technological challenge
 s.</span></span></p>
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