BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Muscat BEGIN:DAYLIGHT DTSTART:20380119T071407 TZOFFSETFROM:+0400 TZOFFSETTO:+0400 RRULE:FREQ=YEARLY;BYDAY=3TU;BYMONTH=1 TZNAME:+04 END:DAYLIGHT BEGIN:STANDARD DTSTART:19200101T001848 TZOFFSETFROM:+0341 TZOFFSETTO:+0400 RRULE:FREQ=YEARLY;BYDAY=1TH;BYMONTH=1 TZNAME:+04 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20251120T101022Z UID:1936BF54-D4E2-470D-9F51-0DCE72ED52A1 DTSTART;TZID=Asia/Muscat:20251117T150000 DTEND;TZID=Asia/Muscat:20251117T160000 DESCRIPTION:This talk will cover practical challenges for cryogenic CMOS de signs for next\ngeneration quantum computing. Starting from system level\, it will detail the design considerations\nfor a non-multiplexed\, semi-au tonomous\, transmon qubit state controller (QSC) implemented in\n14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital\ nprocessor that supports waveform generation and phase rotation operations combined with a low\npower current-mode single sideband upconversion I/Q mixer-based RF arbitrary waveform\ngenerator (AWG). Implemented in 14nm CM OS FinFET technology\, the QSC generates control\nsignals in its target 4. 5GHz to 5.5 GHz frequency range\, achieving an SFDR > 50dB for a signal\nb andwidth of 500MHz. With the controller operating in the 4K stage of a cry ostat and connected\nto a transmon qubit in the cryostat’s millikelvin s tage\, measured transmon T1 and T2 coherence\ntimes were 75.5μS and 73 μ S\, respectively\, in each case comparable to results achieved using\nconv entional room temperature controls. In further tests with transmons\, a qu bit-limited error rate\nof 7.76x10-4 per Clifford gate is achieved\, again comparable to results achieved using room\ntemperature controls. The QSC ’s maximum RF output power is -18 dBm\, and power dissipation\nper qubit under active control is 23mW. An improved\, low power design version usin g end to end\ncurrent mode design that achieves half of this power will al so be presented to demonstrate ultra-\nlow power scaling using current mod e techniques.\n\nSpeaker(s): Dr. Sudipto Chakraborty\n\n Engineering and S cience Building (ESB)\, American University of Sharjah (AUS)\, Sharjah\, U nited Arab Emirates\, United Arab Emirates LOCATION: Engineering and Science Building (ESB)\, American University of S harjah (AUS)\, Sharjah\, United Arab Emirates\, United Arab Emirates ORGANIZER:g00101119@aus.edu SEQUENCE:12 SUMMARY:Challenges and opportunities for ultra-low power design for quantum computing applications URL;VALUE=URI:https://events.vtools.ieee.org/m/505813 X-ALT-DESC:Description: <br /><p>This talk will cover practical challenges for cryogenic CMOS designs for next<br>generation quantum computing. Start ing from system level\, it will detail the design considerations<br>for a non-multiplexed\, semi-autonomous\, transmon qubit state controller (QSC) implemented in<br>14nm CMOS FinFET technology. The QSC includes an augment ed general-purpose digital<br>processor that supports waveform generation and phase rotation operations combined with a low<br>power current-mode si ngle sideband upconversion I/Q mixer-based RF arbitrary waveform<br>genera tor (AWG). Implemented in 14nm CMOS FinFET technology\, the QSC generates control<br>signals in its target 4.5GHz to 5.5 GHz frequency range\, achie ving an SFDR &gt\; 50dB for a signal<br>bandwidth of 500MHz. With the cont roller operating in the 4K stage of a cryostat and connected<br>to a trans mon qubit in the cryostat&rsquo\;s millikelvin stage\, measured transmon T 1 and T2 coherence<br>times were 75.5&mu\;S and 73 &mu\;S\, respectively\, in each case comparable to results achieved using<br>conventional room te mperature controls. In further tests with transmons\, a qubit-limited erro r rate<br>of 7.76x10-4 per Clifford gate is achieved\, again comparable to results achieved using room<br>temperature controls. The QSC&rsquo\;s max imum RF output power is -18 dBm\, and power dissipation<br>per qubit under active control is 23mW. An improved\, low power design version using end to end<br>current mode design that achieves half of this power will also b e presented to demonstrate ultra-<br>low power scaling using current mode techniques.</p> END:VEVENT END:VCALENDAR