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DTSTAMP:20251008T123337Z
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DTSTART;TZID=America/Chicago:20251029T160000
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DESCRIPTION:Abstract: Latest SerDes Technologies such as 200G Ethernet\, PC
 Ie Gen 7\, etc. — A Signal Integrity Perspective\n\nAs SerDes technologi
 es push the boundaries of data rates—reaching 200G Ethernet\, PCIe Gen 7
 \, and beyond—Signal Integrity (SI) becomes a critical factor in ensurin
 g reliable high-speed communication. This talk focuses on the latest advan
 cements in SerDes and their implications for SI across system design\, PCB
  layout\, and interconnect strategies.\n\nWe will explore how PAM4 modulat
 ion\, multi-level signaling\, and lane aggregation impact channel performa
 nce\, and how engineers are addressing challenges like crosstalk\, return 
 loss\, jitter\, and inter-symbol interference (ISI). Special attention wil
 l be given to equalization techniques\, FEC\, and advanced simulation mode
 ls that help predict and mitigate SI issues in real-world designs.\n\nKey 
 topics include:\n\n- SI challenges in 200G Ethernet and PCIe Gen 7\n- Impa
 ct of connector and via design on high-speed channels\n- Role of materials
 \, stack-up\, and routing in maintaining signal fidelity\n- Measurement an
 d validation techniques: TDR\, S-parameters\, eye diagrams\n- Co-design st
 rategies for SerDes PHYs and PCB interconnects\n\nThis session is ideal fo
 r hardware designers\, SI engineers\, and system architects looking to sta
 y ahead in the rapidly evolving landscape of high-speed serial interfaces.
 \n\nSpeaker(s): Randy\, \n\nVirtual: https://events.vtools.ieee.org/m/5058
 40
LOCATION:Virtual: https://events.vtools.ieee.org/m/505840
ORGANIZER:balaji.sankarshanan@ieee.org
SEQUENCE:35
SUMMARY:5th Annual IEEE Midwest PCB Fest 2025!! Part 2 "Latest SerDes techn
 ologies such as 200G Ethernet\, PCIe Gen 7\, etc"
URL;VALUE=URI:https://events.vtools.ieee.org/m/505840
X-ALT-DESC:Description: <br /><h2><strong>Abstract: Latest SerDes Technolog
 ies such as 200G Ethernet\, PCIe Gen 7\, etc. &mdash\; A Signal Integrity 
 Perspective</strong></h2>\n<p>As SerDes technologies push the boundaries o
 f data rates&mdash\;reaching <strong>200G Ethernet</strong>\, <strong>PCIe
  Gen 7</strong>\, and beyond&mdash\;<strong>Signal Integrity (SI)</strong>
  becomes a critical factor in ensuring reliable high-speed communication. 
 This talk focuses on the latest advancements in SerDes and their implicati
 ons for SI across system design\, PCB layout\, and interconnect strategies
 .</p>\n<p>We will explore how <strong>PAM4 modulation</strong>\, <strong>m
 ulti-level signaling</strong>\, and <strong>lane aggregation</strong> impa
 ct channel performance\, and how engineers are addressing challenges like 
 <strong>crosstalk</strong>\, <strong>return loss</strong>\, <strong>jitter
 </strong>\, and <strong>inter-symbol interference (ISI)</strong>. Special 
 attention will be given to <strong>equalization techniques</strong>\, <str
 ong>FEC</strong>\, and <strong>advanced simulation models</strong> that he
 lp predict and mitigate SI issues in real-world designs.</p>\n<p>Key topic
 s include:</p>\n<ul>\n<li>SI challenges in 200G Ethernet and PCIe Gen 7</l
 i>\n<li>Impact of connector and via design on high-speed channels</li>\n<l
 i>Role of materials\, stack-up\, and routing in maintaining signal fidelit
 y</li>\n<li>Measurement and validation techniques: TDR\, S-parameters\, ey
 e diagrams</li>\n<li>Co-design strategies for SerDes PHYs and PCB intercon
 nects</li>\n</ul>\n<p>This session is ideal for hardware designers\, SI en
 gineers\, and system architects looking to stay ahead in the rapidly evolv
 ing landscape of high-speed serial interfaces.</p>
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