BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Taipei BEGIN:STANDARD DTSTART:19790930T230000 TZOFFSETFROM:+0900 TZOFFSETTO:+0800 TZNAME:CST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20251009T082923Z UID:B7A3B514-9D95-491A-9FE3-FD34DDB349D5 DTSTART;TZID=Asia/Taipei:20251009T133000 DTEND;TZID=Asia/Taipei:20251009T150000 DESCRIPTION:This talk presents an overview of the evolving landscape and ro admap of 2.5D and 3D heterogeneous integration technologies\, which are re shaping the future of semiconductor design and system architecture. As dev ice scaling approaches its physical and economic limits\, advanced packagi ng and vertical integration have emerged as key enablers for achieving hig her performance\, energy efficiency\, and functional density.\n\nThe prese ntation will first review the current state of 2.5D and 3D integration\, i ncluding silicon interposers\, through-silicon vias (TSVs)\, hybrid bondin g\, and advanced chiplet-based architectures. These technologies enable th e integration of logic\, memory\, analog\, and power components within a s ingle package\, drastically reducing interconnect parasitics and improving bandwidth and power efficiency.\n\nParticular emphasis will be placed on the emerging opportunities for power conversion within heterogeneous syste ms. With the increasing demand for high-current\, low-voltage power delive ry in AI\, high-performance computing (HPC)\, and data center applications \, 3D integration offers new design paradigms for embedding power manageme nt circuits closer to the load. This reduces power loss\, improves transie nt response\, and enhances overall system reliability.\n\nThe talk will co nclude with a forward-looking roadmap highlighting research and industrial trends in 3D heterogeneous integration — including materials innovation \, thermal management\, design automation\, and standardization efforts — and how these advancements open new pathways for energy-efficient\, hi gh-performance system design across next-generation electronic platforms.\ n\n[] [] []\n\nSpeaker(s): Geert Van der Plas\n\nTainan\, T'ai-wan\, Taiwa n LOCATION:Tainan\, T'ai-wan\, Taiwan ORGANIZER:z11008001@ncku.edu.tw SEQUENCE:72 SUMMARY:3D heterogeneous integration: 2.5D and 3D integration landscape and roadmap\, opportunities for power conversion URL;VALUE=URI:https://events.vtools.ieee.org/m/506018 X-ALT-DESC:Description: <br /><p data-start="128" data-end="566">This talk presents an overview of the evolving landscape and roadmap of 2.5D and 3D heterogeneous integration technologies\, which are reshaping the future of semiconductor design and system architecture. As device scaling approache s its physical and economic limits\, advanced packaging and vertical integ ration have emerged as key enablers for achieving higher performance\, ene rgy efficiency\, and functional density.</p>\n<p data-start="568" data-end ="977">The presentation will first review the current state of 2.5D and 3D integration\, including silicon interposers\, through-silicon vias (TSVs) \, hybrid bonding\, and advanced chiplet-based architectures. These techno logies enable the integration of logic\, memory\, analog\, and power compo nents within a single package\, drastically reducing interconnect parasiti cs and improving bandwidth and power efficiency.</p>\n<p data-start="979" data-end="1441">Particular emphasis will be placed on the emerging opportu nities for power conversion within heterogeneous systems. With the increas ing demand for high-current\, low-voltage power delivery in AI\, high-perf ormance computing (HPC)\, and data center applications\, 3D integration of fers new design paradigms for embedding power management circuits closer t o the load. This reduces power loss\, improves transient response\, and en hances overall system reliability.</p>\n<p data-start="1443" data-end="182 6" data-is-last-node="" data-is-only-node="">The talk will conclude with a forward-looking roadmap highlighting research and industrial trends in 3D heterogeneous integration &mdash\; including materials innovation\, therm al management\, design automation\, and standardization efforts &mdash\; a nd how these advancements open new pathways for energy-efficient\, high-pe rformance system design across next-generation electronic platforms.</p>\n <p data-start="1443" data-end="1826" data-is-last-node="" data-is-only-nod e=""><img src="https://events.vtools.ieee.org/vtools_ui/media/display/73dd 0e1e-5992-4501-b425-3d422324b3d0" alt="" width="324" height="243">&nbsp\;< img src="https://events.vtools.ieee.org/vtools_ui/media/display/b746b2cb-1 757-471b-b85c-e5be30592fbc" alt="" width="324" height="243">&nbsp\;<img sr c="https://events.vtools.ieee.org/vtools_ui/media/display/92665853-6cae-42 18-83b5-3515e55523ed" alt="" width="324" height="243"></p> END:VEVENT END:VCALENDAR