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PRODID:IEEE vTools.Events//EN
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TZID:Asia/Kolkata
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DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
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BEGIN:VEVENT
DTSTAMP:20251021T113552Z
UID:1B184FC9-2808-43A9-8445-3FFCB8BFFDCA
DTSTART;TZID=Asia/Kolkata:20251108T193000
DTEND;TZID=Asia/Kolkata:20251108T210000
DESCRIPTION:Doherty PAs remain the workhorse for high-efficiency transmitte
 rs operating under high PAPR signals\, yet achieving robust back-off effic
 iency\, bandwidth\, and linearizability requires a disciplined design flow
 . This talk presents a practical\, measurement-anchored methodology for hi
 gh-power Doherty PA design using modern GaN processes. We start by revisit
 ing classical and advanced Doherty architectures—asymmetric\, multi-way\
 , wideband/post-matched\, and transformer-based combiners—highlighting h
 ow impedance inverters\, peaking device sizing\, and bias shaping govern d
 ynamic load modulation. The core of the talk focuses on extracting actiona
 ble targets from fundamental-to-harmonic load-pull: interpreting 2D/3D con
 tours (Pout\, PAE\, gain\, IM3/ACPR)\, tracing Zopt trajectories with powe
 r and frequency\, and reconciling CW and modulated load-pull to set realis
 tic back-off efficiency goals (6–10 dB). We translate these insights int
 o a step-by-step synthesis: allocating main/peaking periphery\, selecting 
 inverter impedance and phase\, co-optimizing harmonic terminations\, and d
 esigning post-matching for bandwidth without sacrificing Doherty action. A
 ttendees will leave with a checklist and design templates that link device
 -level load-pull data to circuit-level choices\, expediting convergence to
  Doherty PAs that deliver high efficiency\, linearizability\, and manufact
 urable performance.\n\nSpeaker(s): Asmita Dani\n\nVirtual: https://events.
 vtools.ieee.org/m/507088
LOCATION:Virtual: https://events.vtools.ieee.org/m/507088
ORGANIZER:ieeemttssbcnitm2k23@gmail.com
SEQUENCE:8
SUMMARY:Design Methodology for High-Power Doherty Power Amplifiers: From Lo
 ad-Pull to Layout
URL;VALUE=URI:https://events.vtools.ieee.org/m/507088
X-ALT-DESC:Description: <br /><div>Doherty PAs remain the workhorse for hig
 h-efficiency transmitters operating under high PAPR signals\, yet achievin
 g robust back-off efficiency\, bandwidth\, and linearizability requires a 
 disciplined design flow. This talk presents a practical\, measurement-anch
 ored methodology for high-power Doherty PA design using modern GaN process
 es. We start by revisiting classical and advanced Doherty architectures&md
 ash\;asymmetric\, multi-way\, wideband/post-matched\, and transformer-base
 d combiners&mdash\;highlighting how impedance inverters\, peaking device s
 izing\, and bias shaping govern dynamic load modulation. The core of the t
 alk focuses on extracting actionable targets from fundamental-to-harmonic 
 load-pull: interpreting 2D/3D contours (Pout\, PAE\, gain\, IM3/ACPR)\, tr
 acing Zopt trajectories with power and frequency\, and reconciling CW and 
 modulated load-pull to set realistic back-off efficiency goals (6&ndash\;1
 0 dB). We translate these insights into a step-by-step synthesis: allocati
 ng main/peaking periphery\, selecting inverter impedance and phase\, co-op
 timizing harmonic terminations\, and designing post-matching for bandwidth
  without sacrificing Doherty action.&nbsp\; Attendees will leave with a ch
 ecklist and design templates that link device-level load-pull data to circ
 uit-level choices\, expediting convergence to Doherty PAs that deliver hig
 h efficiency\, linearizability\, and manufacturable performance. &nbsp\;</
 div>\n<div>&nbsp\;</div>
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