BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20251107T051410Z
UID:4E896537-A867-4E3D-8C6E-B9BFE39EACBA
DTSTART;TZID=Asia/Kolkata:20251016T155500
DTEND;TZID=Asia/Kolkata:20251017T155700
DESCRIPTION:Event Description:\n\nThe Cadence Digital Flow Competition is a
 n exciting and competitive event designed to challenge and inspire student
 s in the field of VLSI Design and Digital IC Design Flow. Hosted by [Inser
 t Department/Institute if applicable]\, this competition provides a unique
  platform for participants to demonstrate their skills in digital design m
 ethodologies using industry-standard EDA tools from Cadence.\n\nThis compe
 tition aims to bridge the gap between academic learning and real-world VLS
 I design practices by engaging students in hands-on problem-solving\, tool
  usage\, and flow optimization. Participants will work through various sta
 ges of the digital flow—covering RTL design\, synthesis\, floorplanning\
 , placement\, routing\, and verification.\n\nKey Objectives:\n\n-\nEnhance
  understanding of end-to-end digital design flows\n\n-\nProvide hands-on e
 xperience with Cadence tools\n\n-\nEncourage innovation and practical appl
 ication of VLSI concepts\n\n-\nPrepare students for careers in semiconduct
 or and chip design industries\n\nWhether you&#39;re an aspiring chip designer 
 or a VLSI enthusiast\, the Cadence Digital Flow Competition is your chance
  to learn\, compete\, and showcase your technical prowess in one of the mo
 st critical domains of electronics engineering.\n\nCo-sponsored by: BITM\n
 \nBallari\, Karnataka\, India\, 583104
LOCATION:Ballari\, Karnataka\, India\, 583104
ORGANIZER:abdulbitm@ieee.org
SEQUENCE:22
SUMMARY:Cadence Digital Flow Competition
URL;VALUE=URI:https://events.vtools.ieee.org/m/507325
X-ALT-DESC:Description: &lt;br /&gt;&lt;p data-start=&quot;104&quot; data-end=&quot;126&quot;&gt;&lt;strong da
 ta-start=&quot;104&quot; data-end=&quot;126&quot;&gt;Event Description:&lt;/strong&gt;&lt;/p&gt;\n&lt;p data-sta
 rt=&quot;128&quot; data-end=&quot;536&quot;&gt;The &lt;strong data-start=&quot;132&quot; data-end=&quot;168&quot;&gt;Cadenc
 e Digital Flow Competition&lt;/strong&gt; is an exciting and competitive event d
 esigned to challenge and inspire students in the field of &lt;strong data-sta
 rt=&quot;265&quot; data-end=&quot;307&quot;&gt;VLSI Design and Digital IC Design Flow&lt;/strong&gt;. H
 osted by [Insert Department/Institute if applicable]\, this competition pr
 ovides a unique platform for participants to demonstrate their skills in &lt;
 strong data-start=&quot;456&quot; data-end=&quot;535&quot;&gt;digital design methodologies using 
 industry-standard EDA tools from Cadence&lt;/strong&gt;.&lt;/p&gt;\n&lt;p data-start=&quot;538
 &quot; data-end=&quot;876&quot;&gt;This competition aims to bridge the gap between academic 
 learning and real-world VLSI design practices by engaging students in hand
 s-on problem-solving\, tool usage\, and flow optimization. Participants wi
 ll work through various stages of the digital flow&amp;mdash\;covering RTL des
 ign\, synthesis\, floorplanning\, placement\, routing\, and verification.&lt;
 /p&gt;\n&lt;p data-start=&quot;878&quot; data-end=&quot;893&quot;&gt;Key Objectives:&lt;/p&gt;\n&lt;ul data-star
 t=&quot;894&quot; data-end=&quot;1142&quot;&gt;\n&lt;li data-start=&quot;894&quot; data-end=&quot;952&quot;&gt;\n&lt;p data-st
 art=&quot;896&quot; data-end=&quot;952&quot;&gt;Enhance understanding of end-to-end digital desig
 n flows&lt;/p&gt;\n&lt;/li&gt;\n&lt;li data-start=&quot;953&quot; data-end=&quot;1001&quot;&gt;\n&lt;p data-start=&quot;
 955&quot; data-end=&quot;1001&quot;&gt;Provide hands-on experience with Cadence tools&lt;/p&gt;\n&lt;
 /li&gt;\n&lt;li data-start=&quot;1002&quot; data-end=&quot;1067&quot;&gt;\n&lt;p data-start=&quot;1004&quot; data-en
 d=&quot;1067&quot;&gt;Encourage innovation and practical application of VLSI concepts&lt;/
 p&gt;\n&lt;/li&gt;\n&lt;li data-start=&quot;1068&quot; data-end=&quot;1142&quot;&gt;\n&lt;p data-start=&quot;1070&quot; da
 ta-end=&quot;1142&quot;&gt;Prepare students for careers in semiconductor and chip desig
 n industries&lt;/p&gt;\n&lt;/li&gt;\n&lt;/ul&gt;\n&lt;p data-start=&quot;1144&quot; data-end=&quot;1381&quot;&gt;Wheth
 er you&#39;re an aspiring chip designer or a VLSI enthusiast\, the &lt;strong dat
 a-start=&quot;1211&quot; data-end=&quot;1247&quot;&gt;Cadence Digital Flow Competition&lt;/strong&gt; i
 s your chance to learn\, compete\, and showcase your technical prowess in 
 one of the most critical domains of electronics engineering.&lt;/p&gt;
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