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DTSTART:20260308T030000
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DTSTAMP:20251112T024927Z
UID:4956DB74-D573-481D-BF5C-0800D5AE2338
DTSTART;TZID=America/Los_Angeles:20251112T090000
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DESCRIPTION:This webinar will guide you through the design of a 6GHz LC vol
 tage-controlled oscillator (VCO) using many of the advanced capabilities o
 f the Siemens Solido Design Environment and Solido SPICE simulator. The pr
 esentations will include a useful walkthrough of a practical high-impact R
 F design example including TestBench setup in the Solido Design Environmen
 t\, simulations with Solido SPICE\, and examining results via the Solido W
 aveform Analyzer. You&#39;ll learn to conduct advanced RF analyses to characte
 rize key metrics such as:\n\n- Current consumption\n- KVCO (VCO gain)\n- K
 VDD (supply rejection)\n- Phase noise using HB and PSS analysis\n\nAdditio
 nally\, we&#39;ll spotlight Solido Design Environment features such as:\n\n- T
 rimming\n- Corner group setup\n- PVTMC Verifier\n- Streamlined report gene
 ration\n\nFinally\, we’ll open the floor to a live Q&amp;A session\, providi
 ng you with access to experts in analog/RF design\, verification\, and var
 iation.\n\nWhy Attend?\n\n-\nBoost Productivity:\n\n-\nDiscover how the So
 lido Design Environment and related tools seamlessly integrate to streamli
 ne analog/RF design and verification.\n\n-\nGain Expert Insights:\n\n-\nLe
 arn from engineers actively designing and verifying real-world VCOs.\n\n-\
 nExplore Advanced Tools:\n\n-\nSee how Solido SPICE\, Solido Design Enviro
 nment\, and Solido Waveform Analyzer provide enhanced accuracy and perform
 ance.\n\nCo-sponsored by: Siemens EDA\n\nSpeaker(s): Etienne César\, \n\n
 Virtual: https://events.vtools.ieee.org/m/507450
LOCATION:Virtual: https://events.vtools.ieee.org/m/507450
ORGANIZER:wedge@ieee.org
SEQUENCE:34
SUMMARY:Mastering 6GHz LC VCO Design and Characterization
URL;VALUE=URI:https://events.vtools.ieee.org/m/507450
X-ALT-DESC:Description: &lt;br /&gt;&lt;p style=&quot;line-height: 115%\;&quot;&gt;&amp;nbsp\;&lt;/p&gt;\n&lt;
 p style=&quot;line-height: 115%\;&quot;&gt;&lt;span style=&quot;font-family: &#39;Arial&#39;\,sans-seri
 f\;&quot;&gt;This webinar will guide you through the design of a 6GHz LC voltage-c
 ontrolled oscillator (VCO) using many of the advanced capabilities of the 
 Siemens Solido Design Environment and Solido SPICE simulator. The presenta
 tions will include a useful walkthrough of a practical high-impact RF desi
 gn example including TestBench setup in the&lt;/span&gt;&lt;span style=&quot;font-family
 : &#39;Arial&#39;\,sans-serif\;&quot;&gt; Solido Design Environment\, simulations with Sol
 ido SPICE\, and examining results via the Solido Waveform Analyzer. You&#39;ll
  learn to conduct advanced RF analyses to characterize key metrics such as
 :&lt;/span&gt;&lt;/p&gt;\n&lt;ul type=&quot;disc&quot;&gt;\n&lt;li class=&quot;MsoNormal&quot; style=&quot;mso-margin-to
 p-alt: auto\; mso-margin-bottom-alt: auto\; line-height: 115%\; mso-list: 
 l0 level1 lfo1\; tab-stops: list .5in\;&quot;&gt;&lt;span style=&quot;font-family: &#39;Arial&#39;
 \,sans-serif\; mso-fareast-font-family: &#39;Times New Roman&#39;\;&quot;&gt;Current consu
 mption&lt;/span&gt;&lt;/li&gt;\n&lt;li class=&quot;MsoNormal&quot; style=&quot;mso-margin-top-alt: auto\
 ; mso-margin-bottom-alt: auto\; line-height: 115%\; mso-list: l0 level1 lf
 o1\; tab-stops: list .5in\;&quot;&gt;&lt;span style=&quot;font-family: &#39;Arial&#39;\,sans-serif
 \; mso-fareast-font-family: &#39;Times New Roman&#39;\;&quot;&gt;K&lt;sub&gt;VCO&lt;/sub&gt; (VCO gain
 )&lt;/span&gt;&lt;/li&gt;\n&lt;li class=&quot;MsoNormal&quot; style=&quot;mso-margin-top-alt: auto\; mso
 -margin-bottom-alt: auto\; line-height: 115%\; mso-list: l0 level1 lfo1\; 
 tab-stops: list .5in\;&quot;&gt;&lt;span style=&quot;font-family: &#39;Arial&#39;\,sans-serif\; ms
 o-fareast-font-family: &#39;Times New Roman&#39;\;&quot;&gt;K&lt;sub&gt;VDD&lt;/sub&gt; (supply reject
 ion)&lt;/span&gt;&lt;/li&gt;\n&lt;li class=&quot;MsoNormal&quot; style=&quot;mso-margin-top-alt: auto\; 
 mso-margin-bottom-alt: auto\; line-height: 115%\; mso-list: l0 level1 lfo1
 \; tab-stops: list .5in\;&quot;&gt;&lt;span style=&quot;font-family: &#39;Arial&#39;\,sans-serif\;
  mso-fareast-font-family: &#39;Times New Roman&#39;\;&quot;&gt;Phase noise using HB and PS
 S analysis&lt;/span&gt;&lt;/li&gt;\n&lt;/ul&gt;\n&lt;p style=&quot;line-height: 115%\;&quot;&gt;&lt;span style=
 &quot;font-family: &#39;Arial&#39;\,sans-serif\;&quot;&gt;Additionally\, we&#39;ll spotlight Solido
  Design Environment features such as:&lt;/span&gt;&lt;/p&gt;\n&lt;ul type=&quot;disc&quot;&gt;\n&lt;li cl
 ass=&quot;MsoNormal&quot; style=&quot;mso-margin-top-alt: auto\; mso-margin-bottom-alt: a
 uto\; line-height: 115%\; mso-list: l1 level1 lfo1\; tab-stops: list .5in\
 ;&quot;&gt;&lt;span style=&quot;font-family: &#39;Arial&#39;\,sans-serif\; mso-fareast-font-family
 : &#39;Times New Roman&#39;\;&quot;&gt;Trimming&lt;/span&gt;&lt;/li&gt;\n&lt;li class=&quot;MsoNormal&quot; style=&quot;
 mso-margin-top-alt: auto\; mso-margin-bottom-alt: auto\; line-height: 115%
 \; mso-list: l1 level1 lfo1\; tab-stops: list .5in\;&quot;&gt;&lt;span style=&quot;font-fa
 mily: &#39;Arial&#39;\,sans-serif\; mso-fareast-font-family: &#39;Times New Roman&#39;\;&quot;&gt;
 Corner group setup&lt;/span&gt;&lt;/li&gt;\n&lt;li class=&quot;MsoNormal&quot; style=&quot;mso-margin-to
 p-alt: auto\; mso-margin-bottom-alt: auto\; line-height: 115%\; mso-list: 
 l1 level1 lfo1\; tab-stops: list .5in\;&quot;&gt;&lt;span style=&quot;font-family: &#39;Arial&#39;
 \,sans-serif\; mso-fareast-font-family: &#39;Times New Roman&#39;\;&quot;&gt;PVTMC Verifie
 r&lt;/span&gt;&lt;/li&gt;\n&lt;li class=&quot;MsoNormal&quot; style=&quot;mso-margin-top-alt: auto\; mso
 -margin-bottom-alt: auto\; line-height: 115%\; mso-list: l1 level1 lfo1\; 
 tab-stops: list .5in\;&quot;&gt;&lt;span style=&quot;font-family: &#39;Arial&#39;\,sans-serif\; ms
 o-fareast-font-family: &#39;Times New Roman&#39;\;&quot;&gt;Streamlined report generation&lt;
 /span&gt;&lt;/li&gt;\n&lt;/ul&gt;\n&lt;p style=&quot;line-height: 115%\;&quot;&gt;&lt;span style=&quot;font-famil
 y: &#39;Arial&#39;\,sans-serif\;&quot;&gt;Finally\, we&amp;rsquo\;ll open the floor to a live 
 Q&amp;amp\;A session\, providing you with access to experts in analog/RF desig
 n\, verification\, and variation.&lt;/span&gt;&lt;/p&gt;\n&lt;p style=&quot;line-height: 115%\
 ;&quot;&gt;&amp;nbsp\;&lt;/p&gt;\n&lt;p style=&quot;line-height: 115%\;&quot;&gt;&lt;strong&gt;&lt;span style=&quot;font-f
 amily: &#39;Arial&#39;\,sans-serif\;&quot;&gt;Why Attend?&lt;/span&gt;&lt;/strong&gt;&lt;/p&gt;\n&lt;ul&gt;\n&lt;li c
 lass=&quot;MsoNormal&quot; style=&quot;mso-margin-top-alt: auto\; mso-margin-bottom-alt: 
 auto\; line-height: 115%\; mso-list: l0 level1 lfo1\; tab-stops: list .5in
 \;&quot;&gt;\n&lt;h5&gt;&lt;strong&gt;&lt;span style=&quot;font-family: &#39;Arial&#39;\,sans-serif\; mso-fare
 ast-font-family: &#39;Times New Roman&#39;\;&quot;&gt;Boost Productivity:&amp;nbsp\;&lt;/span&gt;&lt;/s
 trong&gt;&lt;/h5&gt;\n&lt;ul&gt;\n&lt;li class=&quot;MsoNormal&quot; style=&quot;mso-margin-top-alt: auto\;
  mso-margin-bottom-alt: auto\; line-height: 115%\; mso-list: l0 level1 lfo
 1\; tab-stops: list .5in\;&quot;&gt;\n&lt;h5&gt;&lt;span style=&quot;font-family: &#39;Arial&#39;\,sans-
 serif\; mso-fareast-font-family: &#39;Times New Roman&#39;\;&quot;&gt;Discover how the Sol
 ido Design Environment and related tools seamlessly integrate to streamlin
 e analog/RF design and verification.&lt;/span&gt;&lt;/h5&gt;\n&lt;/li&gt;\n&lt;/ul&gt;\n&lt;/li&gt;\n&lt;li
  class=&quot;MsoNormal&quot; style=&quot;mso-margin-top-alt: auto\; mso-margin-bottom-alt
 : auto\; line-height: 115%\; mso-list: l0 level1 lfo1\; tab-stops: list .5
 in\;&quot;&gt;\n&lt;h5&gt;&lt;strong&gt;&lt;span style=&quot;font-family: &#39;Arial&#39;\,sans-serif\; mso-fa
 reast-font-family: &#39;Times New Roman&#39;\;&quot;&gt;Gain Expert Insights:&amp;nbsp\;&lt;/span
 &gt;&lt;/strong&gt;&lt;/h5&gt;\n&lt;ul&gt;\n&lt;li class=&quot;MsoNormal&quot; style=&quot;mso-margin-top-alt: au
 to\; mso-margin-bottom-alt: auto\; line-height: 115%\; mso-list: l0 level1
  lfo1\; tab-stops: list .5in\;&quot;&gt;\n&lt;h5&gt;&lt;span style=&quot;font-family: &#39;Arial&#39;\,s
 ans-serif\; mso-fareast-font-family: &#39;Times New Roman&#39;\;&quot;&gt;Learn from engin
 eers actively designing and verifying real-world VCOs.&lt;/span&gt;&lt;/h5&gt;\n&lt;/li&gt;\
 n&lt;/ul&gt;\n&lt;/li&gt;\n&lt;li&gt;\n&lt;h5&gt;&lt;span style=&quot;font-family: Arial\, sans-serif\; fo
 nt-size: 10pt\;&quot;&gt;&lt;strong&gt;&lt;span style=&quot;font-family: Arial\, sans-serif\; co
 lor: black\;&quot;&gt;Explore Advanced Tools:&lt;/span&gt;&lt;/strong&gt;&lt;span style=&quot;font-fam
 ily: Arial\, sans-serif\; color: black\;&quot;&gt;&amp;nbsp\;&lt;/span&gt;&lt;/span&gt;&lt;/h5&gt;\n&lt;ul&gt;
 \n&lt;li style=&quot;font-size: 10pt\;&quot;&gt;\n&lt;h5&gt;&lt;span style=&quot;font-family: Arial\, sa
 ns-serif\; font-size: 10pt\;&quot;&gt;&lt;span style=&quot;font-family: Arial\, sans-serif
 \; color: black\;&quot;&gt;See how Solido SPICE\, Solido Design Environment\, and 
 Solido Waveform Analyzer provide enhanced accuracy and performance.&lt;/span&gt;
 &lt;/span&gt;&lt;/h5&gt;\n&lt;/li&gt;\n&lt;/ul&gt;\n&lt;/li&gt;\n&lt;/ul&gt;\n&lt;p&gt;&amp;nbsp\;&lt;/p&gt;\n&lt;p&gt;&amp;nbsp\;&lt;/p&gt;
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